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CY7C1486V33-167BX PDF预览

CY7C1486V33-167BX

更新时间: 2024-11-08 21:14:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
31页 528K
描述
Application Specific SRAM, 1MX72, 3.4ns, CMOS, PBGA209

CY7C1486V33-167BX 技术参数

生命周期:Obsolete包装说明:BGA, BGA209,11X19,40
Reach Compliance Code:compliant风险等级:5.84
最长访问时间:3.4 ns最大时钟频率 (fCLK):167 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B209
内存密度:75497472 bit内存集成电路类型:APPLICATION SPECIFIC SRAM
内存宽度:72端子数量:209
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX72
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA209,11X19,40
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL电源:2.5/3.3,3.3 V
认证状态:Not Qualified最小待机电流:3.14 V
子类别:SRAMs表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOMBase Number Matches:1

CY7C1486V33-167BX 数据手册

 浏览型号CY7C1486V33-167BX的Datasheet PDF文件第2页浏览型号CY7C1486V33-167BX的Datasheet PDF文件第3页浏览型号CY7C1486V33-167BX的Datasheet PDF文件第4页浏览型号CY7C1486V33-167BX的Datasheet PDF文件第5页浏览型号CY7C1486V33-167BX的Datasheet PDF文件第6页浏览型号CY7C1486V33-167BX的Datasheet PDF文件第7页 
CY7C1480V33  
CY7C1482V33  
CY7C1486V33  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Pipelined Sync SRAM  
Functional Description[1]  
Features  
• Supports bus operation up to 250 MHz  
The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM  
integrates 2M x 36/4M x 18/1M × 72 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
• Available speed grades are 250, 200 and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• 3.3V core power supply  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX,  
and BWE), and Global Write (GW). Asynchronous inputs  
include the Output Enable (OE) and the ZZ pin.  
• 2.5V/3.3V I/O operation  
• Fast clock-to-output times  
— 3.0 ns (for 250-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
User-selectable burst counter supporting Intel®  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two or four bytes wide as  
controlled by the byte write control inputs. GW when active  
• Single Cycle Chip Deselect  
• CY7C1480V33, CY7C1482V33 available in  
JEDEC-standard lead-free 100-pin TQFP, lead-free and  
non-lead-free 165-ball FBGA package. CY7C1486V33  
available in lead-free and non-lead-free 209 ball FBGA  
package  
causes all bytes to be written.  
LOW  
The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates  
from a +3.3V core power supply while all outputs may operate  
with either a +2.5 or +3.3V supply. All inputs and outputs are  
JEDEC-standard JESD8-5-compatible.  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
Selection Guide  
250 MHz  
3.0  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
500  
500  
450  
mA  
mA  
120  
120  
120  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05283 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 24, 2006  

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