Datasheet > CY7C1484BV25

CY7C1484BV25

更新时间： 2024-11-10 12:51:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
21页	709K
描述
72-Mbit (2 M Ã 36) Pipelined DCD Sync SRAM

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中文翻译

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CY7C1484BV25 数据手册

CY7C1484BV25

72-Mbit (2 M × 36) Pipelined DCD Sync SRAM

72-Mbit (2

M × 36) Pipelined DCD Sync SRAM

Features

Functional Description

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250 MHz

The CY7C1484BV25 SRAM integrates 2 M × 36 SRAM cells with

advanced synchronous peripheral circuitry and a 2-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive edge triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address pipelining Chip Enable (CE₁), depth expansion

Chip Enables (CE₂and CE₃), Burst Control inputs (ADSC,

ADSP, and ADV), Write Enables (BW_Xand BWE), and Global

Write (GW). Asynchronous inputs include the Output Enable

(OE) and the ZZ pin.

■ Registered inputs and outputs for pipelined operation

■ Optimal for performance (double cycle deselect)

■ Depth expansion without wait state

■ 2.5 V core power supply (V_DD

■ 2.5 V I/O supply (V_DDQ

)

Addresses and chip enables are registered at the rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

Advance pin (ADV).

■ Fast clock to output times

❐ 3.0 ns (for 250 MHz device)

■ Provide high performance 3-1-1-1 access rate

■ User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle. This part supports byte write

operations (see Pin Definitions on page 5 and Truth Table on

page 8 for more information). Write cycles can be one to four

bytes wide as controlled by the byte write control inputs. GW

active LOW causes all bytes to be written. This device

incorporates an additional pipelined enable register, which

delays turning off the output buffers an additional cycle when a

deselect is executed. This feature allows depth expansion

without penalizing system performance.

■ Separate processor and controller address strobes

■ Synchronous self timed writes

■ Asynchronous output enable

■ CY7C1484BV25 available in JEDEC-standard Pb-free 100-pin

TQFP package

■ “ZZ” sleep mode option

Selection Guide

Description

Maximum Access Time

250 MHz Unit

3.0

450

120

Maximum Operating Current

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

Document Number: 001-75258 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 27, 2012

12 3 4 5 6 7...21

中文翻译

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与CY7C1484BV25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1484BV33	CYPRESS	获取价格	72-Mbit (2 M Ã 36) Pipelined DCD Sync SRAM
CY7C1484V25	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-167AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-167AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-167BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-167BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-167BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-167BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-200AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-200AXCT	CYPRESS	获取价格	Cache SRAM, 2MX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-

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