Datasheet > CY7C1484V25-200AXCT

CY7C1484V25-200AXCT

更新时间： 2024-11-08 19:50:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
26页	1104K
描述
Cache SRAM, 2MX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100

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CY7C1484V25-200AXCT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	3 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3/e4
长度：	20 mm	内存密度：	75497472 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
功能数量：	1	端子数量：	100
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	MATTE TIN/NICKEL PALLADIUM GOLD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

CY7C1484V25-200AXCT 数据手册

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CY7C1484V25

CY7C1485V25

72-Mbit (2M x 36/4M x 18) Pipelined

DCD Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1484V25/CY7C1485V25 SRAM integrates 2M x

36/4M x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃), Burst Control inputs (ADSC, ADSP,

and ADV), Write Enables (BW_Xand BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (double cycle deselect)

• Depth expansion without wait state

• 2.5V core power supply (V_DD

)

• 2.5V/1.8V IO supply (V_DDQ

)

• Fast clock-to-output times

— 3.0 ns (for 250-MHz device)

Addresses and chip enables are registered at the rising edge

of clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle. This part supports byte write

operations (see “Pin Definitions” on page 5 and “Truth Table”

on page 8 for further details). Write cycles can be one to four

bytes wide, as controlled by the byte write control inputs. GW

active LOW causes all bytes to be written. This device incor-

porates an additional pipelined enable register, which delays

turning off the output buffers an additional cycle when a

deselect is executed. This feature allows depth expansion

without penalizing system performance.

• Asynchronous output enable

• CY7C1484V25, CY7C1485V25 available in JEDEC-

standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free

165-ball FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode option

The CY7C1484V25/CY7C1485V25 operates from a +2.5V

core power supply while all outputs operate with a +2.5V or a

+1.8V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

3.0

450

120

Maximum Operating Current

Maximum CMOS Standby Current

450

400

120

Note

1. For best practices recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation

Document #: 38-05286 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 24, 2007

12 3 4 5 6 7...26

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与CY7C1484V25-200AXCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1484V25-200AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-200BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-200BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-200BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-200BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-250AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-250AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-250BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-250BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1484V25-250BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

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