Datasheet > CY7C1481BV25_13

CY7C1481BV25_13

更新时间： 2024-11-29 12:52:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
21页	713K
描述
72-Mbit (2 M x 36) Flow-Through SRAM

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CY7C1481BV25_13 数据手册

CY7C1481BV25

72-Mbit (2 M × 36) Flow-Through SRAM

72-Mbit (2

M × 36) Flow-Through SRAM

Features

Functional Description

■ Supports 133 MHz bus operations

■ 2 M × 36 common I/O

The CY7C1481BV25 is a 2.5 V, 2 M × 36 synchronous flow

through SRAM designed to interface with high speed

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

counter captures the first address in a burst and increments the

address automatically for the rest of the burst access. All

synchronous inputs are gated by registers controlled by a

positive edge triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, address pipelining

Chip Enable (CE₁), depth expansion Chip Enables (CE₂and

CE₃), Burst Control inputs (ADSC, ADSP, and ADV), Write

■ 2.5 V core power supply (V_DD

■ 2.5 V I/O supply (V_DDQ

)

■ Fast clock to output time

❐ 6.5 ns (133 MHz version)

■ Provide high performance 2-1-1-1 access rate

■ User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

Enables (BW_xand BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

■ Separate processor and controller address strobes

■ Synchronous self timed write

The CY7C1481BV25 enables either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses are initiated with the Processor

Address Strobe (ADSP) or the cache Controller Address Strobe

(ADSC) inputs. Address advancement is controlled by the

Address Advancement (ADV) input.

■ Asynchronous output enable

■ CY7C1481BV25 available in JEDEC standard Pb-free 100-pin

TQFP package

■ IEEE 1149.1 JTAG compatible boundary scan

■ ZZ sleep mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

Advance pin (ADV).

Selection Guide

Description

Maximum Access Time

133 MHz Unit

6.5

305

120

Maximum Operating Current

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

Document Number: 001-74847 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 24, 2013

12 3 4 5 6 7...21

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与CY7C1481BV25_13相关器件

型号	品牌	获取价格	描述	数据表
CY7C1481BV25-133AXI	CYPRESS	获取价格	72-Mbit (2 M x 36) Flow-Through SRAM
CY7C1481BV33	CYPRESS	获取价格	72-Mbit (2 M Ã 36) Flow-Through SRAM
CY7C1481BV33-133AXI	CYPRESS	获取价格	Cache SRAM, 2MX36, 6.5ns, CMOS, PQFP100, TQFP-100
CY7C1481BV33-133AXI	INFINEON	获取价格	Synchronous SRAM
CY7C1481BV33-133BGXI	INFINEON	获取价格	Synchronous SRAM
CY7C1481BV33-133BZI	CYPRESS	获取价格	Cache SRAM, 2MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1481V25	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

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