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CY7C1481V33-100BZXC PDF预览

CY7C1481V33-100BZXC

更新时间： 2024-11-07 05:19:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
30页 1269K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

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中文翻译

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CY7C1481V33-100BZXC 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
Is Samacsys：N最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：17 mm
内存密度：75497472 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：165
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：2MX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.4 mm最小待机电流：3.14 V
子类别：SRAMs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：15 mmBase Number Matches：1

CY7C1481V33-100BZXC 数据手册

 浏览型号CY7C1481V33-100BZXC的Datasheet PDF文件第2页浏览型号CY7C1481V33-100BZXC的Datasheet PDF文件第3页浏览型号CY7C1481V33-100BZXC的Datasheet PDF文件第4页浏览型号CY7C1481V33-100BZXC的Datasheet PDF文件第5页浏览型号CY7C1481V33-100BZXC的Datasheet PDF文件第6页浏览型号CY7C1481V33-100BZXC的Datasheet PDF文件第7页 
CY7C1481V33  
CY7C1483V33  
CY7C1487V33  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Flow-Through SRAM  
Features  
Functional Description[1]  
• Supports 133 MHz bus operations  
• 2M x 36/4M x 18/1M x 72 common IO  
The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V,  
2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM  
designed to interface with high speed microprocessors with  
minimum glue logic. Maximum access delay from clock rise is  
6.5 ns (133 MHz version). A two-bit on-chip counter captures  
the first address in a burst and increments the address  
automatically for the rest of the burst access. All synchronous  
• 3.3V core power supply (VDD  
)
• 2.5V or 3.3V I/O supply (VDDQ  
• Fast clock-to-output times  
— 6.5 ns (133 MHz version)  
)
inputs are gated by registers controlled by  
a
• Provide high-performance 2-1-1-1 access rate  
• User selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
positive-edge-triggered Clock Input (CLK). The synchronous  
inputs include all addresses, all data inputs, address-pipelining  
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and  
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write  
Enables (BWx and BWE), and Global Write (GW).  
Asynchronous inputs include the Output Enable (OE) and the  
ZZ pin.  
• Separate processor and controller address strobes  
• Synchronous self timed write  
• Asynchronous output enable  
• CY7C1481V33, CY7C1483V33 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-ball FBGA package. CY7C1487V33  
available in Pb-free and non-Pb-free 209 ball FBGA  
package  
The CY7C1481V33/CY7C1483V33/CY7C1487V33 allows  
either interleaved or linear burst sequences, selected by the  
MODE input pin. A HIGH selects an interleaved burst  
sequence, while a LOW selects a linear burst sequence. Burst  
accesses can be initiated with the Processor Address Strobe  
(ADSP) or the cache Controller Address Strobe (ADSC)  
inputs. Address advancement is controlled by the Address  
Advancement (ADV) input.  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
) are active. Subsequent  
ADSC  
The CY7C1481V33/CY7C1483V33/CY7C1487V33 operates  
from a +3.3V core power supply while all outputs may operate  
with either a +2.5 or +3.3V supply. All inputs and outputs are  
JEDEC standard JESD8-5 compatible.  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
335  
305  
mA  
mA  
150  
150  
Note  
1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 38-05284 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 01, 2007  
[+] Feedback  
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