Datasheet > CY7C1481V25

CY7C1481V25

更新时间： 2024-11-07 05:19:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	1297K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

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CY7C1481V25 数据手册

CY7C1481V25

CY7C1483V25

CY7C1487V25

72-Mbit (2M x 36/4M x 18/1M x 72)

Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133 MHz bus operations

• 2M x 36/4M x 18/1M x 72 common IO

The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V,

2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive edge triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address pipelining Chip Enable

(CE₁), depth expansion Chip Enables (CE₂and CE₃), Burst

• 2.5V core power supply (V_DD

)

• 2.5V or 1.8V IO supply (V_DDQ

• Fast clock-to-output time

— 6.5 ns (133-MHz version)

)

• Provide high-performance 2-1-1-1 access rate

• User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

Control inputs (ADSC, ADSP, and ADV), Write Enables (BW

and BWE), and Global Write (GW). Asynchronous inputs

• Separate processor and controller address strobes

• Synchronous self timed write

include the Output Enable (OE) and the ZZ pin.

• Asynchronous output enable

The CY7C1481V25/CY7C1483V25/CY7C1487V25 enables

either interleaved or linear burst sequences, selected by the

MODE input pin. A HIGH selects an interleaved burst

sequence, while a LOW selects a linear burst sequence. Burst

accesses can be initiated with the Processor Address Strobe

(ADSP) or the cache Controller Address Strobe

inputs. Address advancement is controlled by the Address

Advancement (ADV) input.

• CY7C1481V25, CY7C1483V25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1487V25

available in Pb-free and non-Pb-free 209-ball FBGA

package

(ADSC)

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1481V25/CY7C1483V25/CY7C1487V25 operates

from a +2.5V core power supply while all outputs may operate

with either a +2.5 or +1.8V supply. All inputs and outputs are

JEDEC-standard JESD8-5-compatible.

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

305

275

120

Note

1. For best practices recommendations, refer to the Cypress application note System Design Guidelines at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05281 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 24, 2007

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与CY7C1481V25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1481V25-100AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-133AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-133AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-133BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-133BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

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