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CY7C1474V33-250BGXC PDF预览

CY7C1474V33-250BGXC

更新时间： 2024-11-06 22:32:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
28页 379K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture

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CY7C1474V33-250BGXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 1.76 MM HEIGHT, LEAD FREE, FBGA-209
针数：209Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.77最长访问时间：3 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：250 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B209
JESD-609代码：e1长度：22 mm
内存密度：75497472 bit内存集成电路类型：ZBT SRAM
内存宽度：72湿度敏感等级：3
功能数量：1端子数量：209
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX72
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA209,11X19,40
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.96 mm
最小待机电流：3.14 V子类别：SRAMs
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
宽度：14 mmBase Number Matches：1

CY7C1474V33-250BGXC 数据手册

 浏览型号CY7C1474V33-250BGXC的Datasheet PDF文件第2页浏览型号CY7C1474V33-250BGXC的Datasheet PDF文件第3页浏览型号CY7C1474V33-250BGXC的Datasheet PDF文件第4页浏览型号CY7C1474V33-250BGXC的Datasheet PDF文件第5页浏览型号CY7C1474V33-250BGXC的Datasheet PDF文件第6页浏览型号CY7C1474V33-250BGXC的Datasheet PDF文件第7页 
CY7C1470V33  
CY7C1472V33  
CY7C1474V33  
PRELIMINARY  
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined  
SRAM with NoBL™ Architecture  
Features  
Functional Description  
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
— Available speed grades are 250, 200, and 167 MHz  
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst  
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.  
They are designed to support unlimited true back-to-back  
Read/Write operations with no wait states. The  
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are  
equipped with the advanced (NoBL) logic required to enable  
consecutive Read/Write operations with data being trans-  
ferred on every clock cycle. This feature dramatically improves  
the throughput of data in systems that require frequent  
Write/Read transitions. The CY7C1470V33, CY7C1472V33,  
and CY7C1474V33 are pin compatible and functionally equiv-  
alent to ZBT devices.  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• Single 3.3V power supply  
• 3.3V/2.5V I/O power supply  
• Fast clock-to-output time  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
— 3.0 ns (for 250-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.4 ns (for 167-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
Write operations are controlled by the Byte Write Selects  
(BWa–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33  
and BWa–BWb for CY7C1472V33) and a Write Enable (WE)  
input. All writes are conducted with on-chip synchronous  
self-timed write circuitry.  
• CY7C1470V33 and CY7C1472V33 available in lead-free  
100 TQFP, and 165-ball fBGA packages. CY7C1474V33  
available in 209-ball fBGA package  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• IEEE 1149.1 JTAG Boundary Scan compatible  
• Burst capability—linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Logic Block Diagram-CY7C1470V33 (2M x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05289 Rev. *E  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised November 23, 2004  
1234567...28

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