Datasheet > 存储 > SRAM> CY7C1475BV25-100BGXC

CY7C1475BV25-100BGXC

更新时间： 2024-11-07 05:19:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
30页	848K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1475BV25-100BGXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA, BGA209,11X19,40
针数：	209	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.8	Is Samacsys：	N
最长访问时间：	8.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	100 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B209	JESD-609代码：	e1
长度：	22 mm	内存密度：	75497472 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	72
湿度敏感等级：	3	功能数量：	1
端子数量：	209	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX72	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA209,11X19,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
电源：	1.8/2.5,2.5 V	认证状态：	Not Qualified
座面最大高度：	1.96 mm	最小待机电流：	2.38 V
子类别：	SRAMs	最大压摆率：	0.275 mA
最大供电电压 (Vsup)：	2.625 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	14 mm	Base Number Matches：	1

CY7C1475BV25-100BGXC 数据手册

浏览型号CY7C1475BV25-100BGXC的Datasheet PDF文件第2页

浏览型号CY7C1475BV25-100BGXC的Datasheet PDF文件第3页

浏览型号CY7C1475BV25-100BGXC的Datasheet PDF文件第4页

浏览型号CY7C1475BV25-100BGXC的Datasheet PDF文件第5页

浏览型号CY7C1475BV25-100BGXC的Datasheet PDF文件第6页

浏览型号CY7C1475BV25-100BGXC的Datasheet PDF文件第7页

CY7C1471BV25

CY7C1473BV25, CY7C1475BV25

72-Mbit (2M x 36/4M x 18/1M x 72)

Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

■ No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25

are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through

burst SRAMs designed specifically to support unlimited true

back-to-back read or write operations without the insertion of

wait states. The CY7C1471BV25, CY7C1473BV25, and

CY7C1475BV25 are equipped with the advanced No Bus

Latency (NoBL) logic required to enable consecutive read or

write operations with data transferred on every clock cycle. This

feature dramatically improves the throughput of data through the

SRAM, especially in systems that require frequent write-read

transitions.

■ Supports up to 133 MHz bus operations with zero wait states

■ Data transfers on every clock

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self timed output buffer control to eliminate the need

to use OE

■ Registered inputs for flow through operation

■ Byte Write capability

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

Clock Enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133-MHz device).

■ 2.5V IO supply (V_DDQ

)

■ Fast clock-to-output times

❐ 6.5 ns (for 133-MHz device)

Write operations are controlled by two or four Byte Write Select

(BW_X) and a Write Enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.

■ Clock Enable (CEN) pin to enable clock and suspend operation

■ Synchronous self timed writes

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide easy bank selection

and output tri-state control. To avoid bus contention, the output

drivers are synchronously tri-stated during the data portion of a

write sequence.

■ Asynchronous Output Enable (OE)

■ CY7C1471BV25, CY7C1473BV25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1475BV25

available in Pb-free and non-Pb-free 209-ball FBGA package.

For best practice recommendations, refer to the Cypress appli-

cation note AN1064, SRAM System Guidelines.

■ Three Chip Enables (CE₁, CE₂, CE₃) for simple depth

expansion.

■ Automatic power down feature available using ZZ mode or CE

deselect.

■ IEEE 1149.1 JTAG Boundary Scan compatible

■ Burst Capability - linear or interleaved burst order

■ Low standby power

Selection Guide

Description

Maximum Access Time

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Operating Current

305

275

Maximum CMOS Standby Current

120

Cypress Semiconductor Corporation

Document #: 001-15013 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 29, 2008

[+] Feedback

12 3 4 5 6 7...30

中文翻译

下载PDF

与CY7C1475BV25-100BGXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1475BV25-100BGXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1475BV25-133BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1475BV25-133BGI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1475BV25-133BGXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1475BV25-133BGXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1475BV33	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475BV33-117BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475BV33-117BGI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475BV33-117BGXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475BV33-117BGXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

与CY7C1475BV25-100BGXC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

16
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1475BV25-100BGXC

CY7C1475BV25-100BGXC 技术参数

CY7C1475BV25-100BGXC 数据手册

与CY7C1475BV25-100BGXC相关器件

与CY7C1475BV25-100BGXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1475BV25-100BGXC

CY7C1475BV25-100BGXC 技术参数

CY7C1475BV25-100BGXC 数据手册

与CY7C1475BV25-100BGXC相关器件

与CY7C1475BV25-100BGXC相关文章

您还可以找

您在本页遇到什么问题？