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CY7C1475V25-100BGI PDF预览

CY7C1475V25-100BGI

更新时间： 2024-09-18 05:19:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
32页 1137K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture

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中文翻译

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CY7C1475V25-100BGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
针数：209Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B209
JESD-609代码：e0长度：22 mm
内存密度：75497472 bit内存集成电路类型：ZBT SRAM
内存宽度：72功能数量：1
端子数量：209字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX72输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA209,11X19,40封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.5/2.5,2.5 V
认证状态：Not Qualified座面最大高度：1.96 mm
最小待机电流：2.38 V子类别：SRAMs
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1475V25-100BGI 数据手册

 浏览型号CY7C1475V25-100BGI的Datasheet PDF文件第2页浏览型号CY7C1475V25-100BGI的Datasheet PDF文件第3页浏览型号CY7C1475V25-100BGI的Datasheet PDF文件第4页浏览型号CY7C1475V25-100BGI的Datasheet PDF文件第5页浏览型号CY7C1475V25-100BGI的Datasheet PDF文件第6页浏览型号CY7C1475V25-100BGI的Datasheet PDF文件第7页 
CY7C1471V25  
CY7C1473V25  
CY7C1475V25  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Flow-ThroughSRAMwithNoBL™Architecture  
Functional Description[1]  
Features  
• No Bus Latency™ (NoBL™) architecture eliminates dead  
cycles between write and read cycles  
The CY7C1471V25, CY7C1473V25, and CY7C1475V25 are  
2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst  
SRAMs designed specifically to support unlimited true  
back-to-back read or write operations without the insertion of  
wait states. The CY7C1471V25, CY7C1473V25, and  
CY7C1475V25 are equipped with the advanced No Bus  
Latency (NoBL) logic required to enable consecutive read or  
write operations with data transferred on every clock cycle.  
This feature dramatically improves the throughput of data  
through the SRAM, especially in systems that require frequent  
write-read transitions.  
• Supportsupto133MHzbusoperationswithzerowaitstates  
• Data is transferred on every clock  
• PincompatibleandfunctionallyequivalenttoZBT™devices  
• Internally self timed output buffer control to eliminate the  
need to use OE  
• Registered inputs for flow through operation  
• Byte Write capability  
• 2.5V/1.8V IO supply (VDDQ  
)
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
• Clock Enable (CEN) pin to enable clock and suspend  
operation  
• Synchronous self timed writes  
Write operations are controlled by two or four Byte Write Select  
(BWX) and a Write Enable (WE) input. All writes are conducted  
with on-chip synchronous self timed write circuitry.  
• Asynchronous Output Enable (OE)  
• CY7C1471V25, CY7C1473V25 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-Ball FBGA package. CY7C1475V25  
available in Pb-free and non-Pb-free 209-Ball FBGA  
package.  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
• Three Chip Enables (CE1, CE2, CE3) for simple depth  
expansion.  
• Automatic power down feature available using ZZ mode or  
CE deselect.  
• IEEE 1149.1 JTAG Boundary Scan compatible  
• Burst Capability - linear or interleaved burst order  
• Low standby power  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
305  
120  
275  
mA  
mA  
120  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 38-05287 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 04, 2007  
1234567...32

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CY7C1475V25-133BGXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
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CY7C1475V25-133BX CYPRESS

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 		ZBT SRAM, 1MX72, 5.5ns, CMOS, PBGA209
CY7C1475V33 CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

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