Datasheet > CY7C1460AV33_12

CY7C1460AV33_12

更新时间： 2024-11-07 12:28:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	1000K
描述
36-Mbit (1 M Ã 36/2 M Ã 18) Pipelined SRAM with NoBLâ¢ Architecture

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CY7C1460AV33_12 数据手册

CY7C1460AV33

CY7C1462AV33

36-Mbit (1 M × 36/2 M × 18)

Pipelined SRAM with NoBL™ Architecture

36-Mbit (1

M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

■ Pin compatible and functionally equivalent to ZBT

The CY7C1460AV33/CY7C1462AV33 are 3.3 V, 1 M × 36/2 M × 18

synchronous pipelined burst SRAMs with No Bus Latency™

(NoBL logic, respectively. They are designed to support

unlimited true back-to-back read/write operations with no wait

states. The CY7C1460AV33/CY7C1462AV33 are equipped with

the advanced (NoBL) logic required to enable consecutive

read/write operations with data being transferred on every clock

cycle. This feature dramatically improves the throughput of data

in systems that require frequent write/read transitions. The

CY7C1460AV33/CY7C1462AV33 are pin compatible and

functionally equivalent to ZBT devices.

■ Supports 250 MHz bus operations with zero wait states

❐ Available speed grades are 250, 200 and 167 MHz

■ Internally self timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte write capability

■ 3.3 V power supply

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle.

■ 3.3 V/2.5 V I/O power supply

■ Fast clock-to-output times

❐ 2.6 ns (for 250 MHz device)

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self timed writes

Write operations are controlled by the byte write selects

(BW_a–BW_dfor CY7C1460AV33 and BW_a–BW_bfor

CY7C1462AV33) and a write enable (WE) input. All writes are

conducted with on-chip synchronous self timed write circuitry.

■ CY7C1460AV33 available in JEDEC-standard Pb-free 100-pin

TQFP and non Pb-free 165-ball FBGA package.

CY7C1462AV33 available in JEDEC-standard Pb-free 100-pin

TQFP.

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tristate control. To avoid bus contention, the

output drivers are synchronously tristated during the data portion

of a write sequence.

■ IEEE 1149.1 JTAG-compatible boundary scan

■ Burst capability – linear or interleaved burst order

■ “ZZ” sleep mode option and stop clock option

Logic Block Diagram – CY7C1460AV33

ADDRESS

A0, A1,

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQ s

DQ P

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document Number: 38-05353 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 5, 2012

12 3 4 5 6 7...31

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与CY7C1460AV33_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1460AV33-167	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1460AV33-167AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1460AV33-167AXCT	CYPRESS	获取价格	ZBT SRAM, 1MX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-
CY7C1460AV33-167AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1460AV33-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1460AV33-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1460AV33-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1460AV33-167BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1460AV33-200	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1460AV33-200AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined

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