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CY7C1460BV25 PDF预览

CY7C1460BV25

更新时间： 2024-09-25 12:23:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 721K
描述
36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture

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CY7C1460BV25 数据手册

 浏览型号CY7C1460BV25的Datasheet PDF文件第2页浏览型号CY7C1460BV25的Datasheet PDF文件第3页浏览型号CY7C1460BV25的Datasheet PDF文件第4页浏览型号CY7C1460BV25的Datasheet PDF文件第5页浏览型号CY7C1460BV25的Datasheet PDF文件第6页浏览型号CY7C1460BV25的Datasheet PDF文件第7页 
CY7C1460BV25  
CY7C1462BV25  
36-Mbit (1 M × 36/2 M × 18)  
Pipelined SRAM with NoBL™ Architecture  
36-Mbit (1  
M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
The  
CY7C1460BV25/CY7C1462BV25  
are  
2.5 V,  
■ Pin-compatible and functionally equivalent to ZBT™  
1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No  
Bus Latency™ (NoBL logic, respectively. They are designed  
to support unlimited true back-to-back read/write operations with  
no wait states. The CY7C1460BV25/CY7C1462BV25 are  
equipped with the advanced NoBL logic required to enable  
consecutive read/write operations with data being transferred on  
every clock cycle. This feature dramatically improves the  
throughput of data in systems that require frequent write/read  
■ Supports 250-MHz bus operations with zero wait states  
❐ Available speed grades is 250 MHz  
■ Internally self-timed output buffer control to eliminate the need  
to use asynchronous OE  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte Write capability  
transitions.  
The  
CY7C1460BV25/CY7C1462BV25  
are  
pin-compatible and functionally equivalent to ZBT devices.  
■ 2.5 V core power supply  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the clock enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle. Write operations are controlled by the byte write selects  
(BWa–BWd for CY7C1460BV25 and BWa–BWb for  
CY7C1462BV25) and a write enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
■ 2.5 V/1.8 V I/O power supply  
■ Fast clock-to-output times  
❐ 2.6 ns (for 250-MHz device)  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self-timed writes  
■ CY7C1460BV25, CY7C1462BV25 available in Pb-free  
165-ball FBGA package and CY7C1462BV25 available in  
JEDEC-standard Pb-free 100-pin TQFP package  
Three synchronous chip enables (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
■ IEEE 1149.1 JTAG-Compatible Boundary Scan  
■ Burst capability – linear or interleaved burst order  
■ “ZZ” sleep mode option and stop clock option  
Logic Block Diagram – CY7C1460BV25  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document Number: 001-74446 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 25, 2012  
1234567...30

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