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CY7C1460KV33-167AXC PDF预览

CY7C1460KV33-167AXC

更新时间： 2024-09-26 19:52:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
31页 2877K
描述
ZBT SRAM, 1MX36, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100

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CY7C1460KV33-167AXC 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LQFP,Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.75其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：37748736 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

CY7C1460KV33-167AXC 数据手册

 浏览型号CY7C1460KV33-167AXC的Datasheet PDF文件第2页浏览型号CY7C1460KV33-167AXC的Datasheet PDF文件第3页浏览型号CY7C1460KV33-167AXC的Datasheet PDF文件第4页浏览型号CY7C1460KV33-167AXC的Datasheet PDF文件第5页浏览型号CY7C1460KV33-167AXC的Datasheet PDF文件第6页浏览型号CY7C1460KV33-167AXC的Datasheet PDF文件第7页 
CY7C1460KV33  
CY7C1460KVE33  
CY7C1462KVE33  
36-Mbit (1M × 36/2M × 18) Pipelined SRAM  
with NoBL™ Architecture (With ECC)  
36-Mbit (1M  
× 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)  
Features  
Functional Description  
■ Pin-compatible and functionally equivalent to Zero Bus  
Turnaround (ZBT™)  
The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are  
3.3 V, 1M × 36, and 2M × 18 synchronous pipelined burst SRAMs  
with No Bus Latency™ (NoBL logic, respectively. They are  
designed to support unlimited true back-to-back read/write  
■ Supports 250-MHz bus operations with zero wait states  
❐ Available speed grades are 250, 200, and 167 MHz  
operations  
with  
no  
wait  
states.  
The  
■ Internally self-timed output buffer control to eliminate the need  
to use asynchronous OE  
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices  
are equipped with the advanced (NoBL) logic required to enable  
consecutive read/write operations with data being transferred on  
every clock cycle. 6  
■ Fully-registered (inputs and outputs) for pipelined operation  
■ Byte write capability  
This feature dramatically improves the throughput of data in  
systems that require frequent write and read transitions. The  
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices  
are pin-compatible and functionally equivalent to ZBT devices.  
■ 3.3-V power supply  
■ 3.3-V/2.5-V I/O power supply  
■ Fast clock-to-output time  
❐ 2.5 ns (for 250-MHz device)  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the clock enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle.  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self-timed writes  
■ CY7C1460KV33,  
CY7C1460KVE33,  
CY7C1462KVE33  
available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free  
and non Pb-free 165-ball FBGA packages  
Write operations are controlled by the byte write selects  
(BWa–BWd  
for  
CY7C1460KV33/CY7C1460KVE33  
and  
■ IEEE 1149.1 JTAG-compatible boundary scan  
■ Burst capability—linear or interleaved burst order  
■ “ZZ” sleep mode option  
BWa–BWb for CY7C1462KVE33) and a write enable (WE) input.  
All writes are conducted with on-chip synchronous self-timed  
write circuitry.  
Three synchronous chip enables (CE1, CE2, and CE3) and an  
asynchronous output enable (OE) enable easy bank selection  
and output tristate control. To avoid bus contention, the output  
drivers are synchronously tristated during the data portion of a  
write sequence.  
■ On-chip Error Correction Code (ECC) to reduce Soft Error Rate  
(SER)  
Selection Guide  
Description  
Maximum access time  
250 MHz  
2.5  
200 MHz  
3.2  
167 MHz Unit  
3.4  
170  
190  
ns  
Maximum operating current  
× 18  
× 36  
220  
190  
mA  
240  
210  
Cypress Semiconductor Corporation  
Document Number: 001-66680 Rev. *K  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 5, 2016  
1234567...31

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