Datasheet > CY7C1460KVE25-167AXC

CY7C1460KVE25-167AXC

更新时间： 2024-09-28 14:56:47

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
32页	824K
描述
Synchronous SRAM with ECC

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CY7C1460KV25/CY7C1462KV25

CY7C1460KVE25/CY7C1462KVE25

36-Mbit (1M × 36/2M × 18)

Pipelined SRAM

with NoBL™ Architecture (With ECC)

36-Mbit (1M

× 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)

Features

Functional Description

The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/

CY7C1462KVE25 are 2.5 V, 1M × 36/2M × 18 synchronous

pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic,

respectively. They are designed to support unlimited true

back-to-back read/write operations with no wait states. The

CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/

CY7C1462KVE25 are equipped with the advanced NoBL logic

required to enable consecutive read/write operations with data

being transferred on every clock cycle. This feature dramatically

improves the throughput of data in systems that require frequent

write/read transitions. The CY7C1460KV25/CY7C1462KV25/

CY7C1460KVE25/CY7C1462KVE25 are pin-compatible and

functionally equivalent to ZBT devices.

■ Pin-compatible and functionally equivalent to ZBT™

■ Supports 250 MHz bus operations with zero wait states

❐ Availablespeedgradesare250MHz, 200MHz, and167MHz

■ Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte Write capability

■ 2.5 V core power supply

■ 2.5 V I/O power supply

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle. Write operations are controlled by the byte write selects

■ Fast clock-to-output times

❐ 2.5 ns (for 250 MHz device)

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

BW_a–BW_d

for

CY7C1460KV25/CY7C1460KVE25

and

■ CY7C1460KV25, CY7C1462KV25, CY7C1460KVE25 and

CY7C1462KVE25 available in JEDEC-standard Pb-free

100-pin TQFP, and Pb-free and non Pb-free 165-ball FBGA

packages.

BW_a–BW_bfor CY7C1462KV25/CY7C1462KVE25 and a write

enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ Burst capability — linear or interleaved burst order

■ “ZZ” sleep mode option

■ On-chip error correction code (ECC) to reduce soft error rate

(SER)

Selection Guide

Description

Maximum access time

250 MHz

2.5

200 MHz

3.2

167 MHz Unit

3.4

170

190

Maximum operating current

× 18

× 36

220

190

240

210

Cypress Semiconductor Corporation

Document Number: 001-66679 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 7, 2018

12 3 4 5 6 7...32

中文翻译

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与CY7C1460KVE25-167AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1460KVE25-200BZXI	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460KVE25-200BZXI	INFINEON	获取价格	Synchronous SRAM with ECC
CY7C1460KVE25-250AXC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460KVE25-250AXC	INFINEON	获取价格	Synchronous SRAM with ECC
CY7C1460KVE33	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460KVE33-167AXI	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460KVE33-167AXI	INFINEON	获取价格	Synchronous SRAM with ECC
CY7C1460KVE33-167BZC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460KVE33-200AXC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460KVE33-200AXC	INFINEON	获取价格	Synchronous SRAM with ECC

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