Datasheet > CY7C1460KVE33-167AXI

CY7C1460KVE33-167AXI

更新时间： 2024-09-28 14:54:39

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
31页	948K
描述
Synchronous SRAM with ECC

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CY7C1460KV33

CY7C1460KVE33

CY7C1462KVE33

36-Mbit (1M × 36/2M × 18) Pipelined SRAM

with NoBL™ Architecture (With ECC)

CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33, 36-Mbit (1M

× 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)

Features

Functional Description

■ Pin-compatible and functionally equivalent to Zero Bus

Turnaround (ZBT™)

The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are

3.3 V, 1M × 36, and 2M × 18 synchronous pipelined burst SRAMs

with No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back read/write

■ Supports 250-MHz bus operations with zero wait states

❐ Available speed grades are 250, 200, and 167 MHz

operations

with

wait

states.

The

■ Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices

are equipped with the advanced (NoBL) logic required to enable

consecutive read/write operations with data being transferred on

every clock cycle.

■ Fully-registered (inputs and outputs) for pipelined operation

■ Byte write capability

This feature dramatically improves the throughput of data in

systems that require frequent write and read transitions. The

CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices

are pin-compatible and functionally equivalent to ZBT devices.

■ 3.3-V power supply

■ 3.3-V/2.5-V I/O power supply

■ Fast clock-to-output time

❐ 2.5 ns (for 250-MHz device)

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle.

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

■ CY7C1460KV33,

CY7C1460KVE33,

CY7C1462KVE33

available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free

and non Pb-free 165-ball FBGA packages

Write operations are controlled by the byte write selects (BW_a–

BW_dfor CY7C1460KV33/CY7C1460KVE33 and BW_a–BW_bfor

CY7C1462KVE33) and a write enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

■ IEEE 1149.1 JTAG-compatible boundary scan

■ Burst capability—linear or interleaved burst order

■ “ZZ” sleep mode option

Three synchronous chip enables (CE₁, CE₂, and CE₃) and an

asynchronous output enable (OE) enable easy bank selection

and output tristate control. To avoid bus contention, the output

drivers are synchronously tristated during the data portion of a

write sequence.

■ On-chip Error Correction Code (ECC) to reduce Soft Error Rate

(SER)

Selection Guide

Description

Maximum access time

250 MHz

2.5

200 MHz

3.2

167 MHz Unit

3.4

170

190

Maximum operating current

× 18

× 36

220

190

240

210

Cypress Semiconductor Corporation

Document Number: 001-66680 Rev. *M

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 28, 2020

12 3 4 5 6 7...31

中文翻译

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与CY7C1460KVE33-167AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1460KVE33-167BZC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460KVE33-200AXC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460KVE33-200AXC	INFINEON	获取价格	Synchronous SRAM with ECC
CY7C1460SV25	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460SV25-167AXC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460SV25-167BZC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460SV25-167BZXC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460SV25-250BZC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1460V25	ETC	获取价格	Memory
CY7C1460V25-167AC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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