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CY7C144AV-20AC PDF预览

CY7C144AV-20AC

更新时间： 2024-01-18 03:27:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
20页 546K
描述
3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM

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中文翻译

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CY7C144AV-20AC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, LCC-68
针数：68Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.71Is Samacsys：N
最长访问时间：20 nsI/O 类型：COMMON
JESD-30 代码：S-PQCC-J68JESD-609代码：e0
长度：24.2316 mm内存密度：65536 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：8
功能数量：1端口数量：2
端子数量：68字数：8192 words
字数代码：8000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：8KX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC68,1.0SQ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大待机电流：0.00005 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.175 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：24.2316 mm
Base Number Matches：1

CY7C144AV-20AC 数据手册

 浏览型号CY7C144AV-20AC的Datasheet PDF文件第3页浏览型号CY7C144AV-20AC的Datasheet PDF文件第4页浏览型号CY7C144AV-20AC的Datasheet PDF文件第5页浏览型号CY7C144AV-20AC的Datasheet PDF文件第7页浏览型号CY7C144AV-20AC的Datasheet PDF文件第8页浏览型号CY7C144AV-20AC的Datasheet PDF文件第9页 
CY7C138AV/144AV/006AV  
CY7C139AV/145AV/016AV  
CY7C007AV/017AV  
prevents the port from setting the interrupt to the winning port.  
Also, an active busy to a port prevents that port from reading  
its own mailbox and, thus, resetting the interrupt to it. If an  
application does not require message passing, do not connect  
the interrupt pin to the processor’s interrupt request input pin.  
The operation of the interrupts and their interaction with Busy  
are summarized in Table 2.  
request a given resource, it sets a latch by writing a zero to a  
semaphore location. The left port then verifies its success in  
setting the latch by reading it. After writing to the semaphore,  
SEM or OE must be deasserted for tSOP before attempting to  
read the semaphore. The semaphore value will be available  
tSWRD + tDOE after the rising edge of the semaphore write. If  
the left port was successful (reads a zero), it assumes control  
of the shared resource, otherwise (reads a one) it assumes the  
right port has control and continues to poll the semaphore.  
When the right side has relinquished control of the semaphore  
(by writing a one), the left side will succeed in gaining control  
of the semaphore. If the left side no longer requires the  
semaphore, a one is written to cancel its request.  
Busy  
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/  
145AV/016AV/017AV provide on-chip arbitration to resolve  
simultaneous memory location access (contention). If both  
ports’ CEs are asserted and an address match occurs within  
t
PS of each other, the busy logic will determine which port has  
Semaphores are accessed by asserting SEM LOW. The SEM  
pin functions as a chip select for the semaphore latches (CE  
must remain HIGH during SEM LOW). A0–2 represents the  
semaphore address. OE and R/W are used in the same  
manner as a normal memory access. When writing or reading  
a semaphore, the other address pins have no effect.  
access. If tPS is violated, one port will definitely gain  
permission to the location, but it is not predictable which port  
will get that permission. BUSY will be asserted tBLA after an  
address match or tBLC after CE is taken LOW.  
Master/Slave  
When writing to the semaphore, only I/O0 is used. If a zero is  
written to the left port of an available semaphore, a one will  
appear at the same semaphore address on the right port. That  
semaphore can now only be modified by the side showing zero  
(the left port in this case). If the left port now relinquishes  
control by writing a one to the semaphore, the semaphore will  
be set to one for both sides. However, if the right port had  
requested the semaphore (written a zero) while the left port  
had control, the right port would immediately own the  
semaphore as soon as the left port released it. Table 3 shows  
sample semaphore operations.  
An M/S pin is provided in order to expand the word width by  
configuring the device as either a master or a slave. The BUSY  
output of the master is connected to the BUSY input of the  
slave. This will allow the device to interface to a master device  
with no external components. Writing to slave devices must be  
delayed until after the BUSY input has settled (tBLC or tBLA),  
otherwise, the slave chip may begin a write cycle during a  
contention situation. When tied HIGH, the M/S pin allows the  
device to be used as a master and, therefore, the BUSY line  
is an output. BUSY can then be used to send the arbitration  
outcome to a slave.  
When reading a semaphore, all data lines output the  
semaphore value. The read value is latched in an output  
register to prevent the semaphore from changing state during  
a write from the other port. If both ports attempt to access the  
semaphore within tSPS of each other, the semaphore will  
definitely be obtained by one side or the other, but there is no  
guarantee which side will control the semaphore.  
Semaphore Operation  
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/  
145AV/016AV/017AV provide eight semaphore latches, which  
are separate from the dual-port memory locations.  
Semaphores are used to reserve resources that are shared  
between the two ports. The state of the semaphore indicates  
that a resource is in use. For example, if the left port wants to  
Document #: 38-06051 Rev. *C  
Page 6 of 20  
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CY7C144V-15JCR CYPRESS

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CY7C144V-25JCR CYPRESS

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 		8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

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