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CY7C1399BN-15VXA

更新时间： 2024-11-06 03:14:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 307K
描述
256K (32K x 8) Static RAM

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CY7C1399BN-15VXA 数据手册

 浏览型号CY7C1399BN-15VXA的Datasheet PDF文件第2页浏览型号CY7C1399BN-15VXA的Datasheet PDF文件第3页浏览型号CY7C1399BN-15VXA的Datasheet PDF文件第4页浏览型号CY7C1399BN-15VXA的Datasheet PDF文件第5页浏览型号CY7C1399BN-15VXA的Datasheet PDF文件第6页浏览型号CY7C1399BN-15VXA的Datasheet PDF文件第7页 
CY7C1399BN  
256K (32K x 8) Static RAM  
expansion is provided by an active LOW Chip Enable (CE) and  
active LOW Output Enable (OE) and tri-state drivers. The  
device has an automatic power-down feature, reducing the  
power consumption by more than 95% when deselected.  
Features  
• Temperature Ranges  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
• Single 3.3V power supply  
• Ideal for low-voltage cache memory applications  
• High speed: 12 ns  
An active LOW Write Enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins is present on the eight data input/output pins.  
• Low active power  
— 180 mW (max.)  
• Low-power alpha immune 6T cell  
• Available in Pb-free and non Pb-free Plastic SOJ and  
TSOP I packages  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. The CY7C1399BN is available in 28-pin  
standard 300-mil-wide SOJ and TSOP Type I packages.  
Functional Description[1]  
The CY7C1399BN is a high-performance 3.3V CMOS Static  
RAM organized as 32,768 words by 8 bits. Easy memory  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
A
A
6
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
WE  
A
7
A
4
A
3
A
8
I/O  
0
I/O  
1
I/O  
2
I/O  
3
I/O  
4
I/O  
5
I/O  
6
25  
24  
INPUT BUFFER  
A
9
A
2
A
10  
23  
22  
A
0
A
1
A
1
A
11  
7
8
9
10  
11  
12  
13  
OE  
A
0
A
2
A
12  
21  
20  
19  
18  
17  
A
3
A
4
A
13  
CE  
I/O  
32K x 8  
ARRAY  
A
5
A
A
14  
6
A
7
7
A
I/O  
I/O  
6
0
8
A
9
I/O  
I/O  
5
1
16  
15  
I/O  
GND  
I/O  
2
4
CE  
WE  
I/O  
14  
3
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Selection Guide  
-12  
12  
-15  
-20  
Maximum Access Time (ns)  
15  
50  
20  
45  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (µA)  
55  
Commercial  
500  
50  
500  
50  
500  
50  
Commercial (L)  
Industrial  
500  
500  
500  
Automotive-A  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06490 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 31, 2006  
[+] Feedback  
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CY7C1399BN-15VXA 替代型号

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