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CY7C1399D-12VXI

更新时间： 2024-11-24 03:13:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 203K
描述
256K (32K x 8) Static RAM

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CY7C1399D-12VXI 数据手册

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CY7C1399D  
PRELIMINARY  
256K (32K x 8) Static RAM  
Features  
Functional Description[1]  
• Pin- and function-compatible with CY7C1399B  
• Single 3.3V power supply  
The CY7C1399D is a high-performance 3.3V CMOS Static  
RAM organized as 32,768 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE) and  
active LOW Output Enable (OE) and tri-state drivers. The  
device has an automatic power-down feature, reducing the  
power consumption when deselected.  
• Ideal for low-voltage cache memory applications  
• High speed  
— tAA = 8 ns  
An active LOW Write Enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins is present on the eight data input/output pins.  
• Low active power  
— ICC = 60 mA @ 10 ns  
• Low CMOS standby power  
— ISB2 = 1.2 mA (“L” Version only)  
• Data Retention at 2.0V  
• Available in 28-SOJ and 28-TSOP I Pb-Free packages  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. The CY7C1399D is available in 28-pin standard  
300-mil-wide SOJ and TSOP Type I Pb-Free packages.  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
A
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
WE  
6
A
A
7
A
4
A
3
8
25  
24  
A
9
A
2
A
10  
A
11  
A
12  
23  
22  
A
1
7
8
9
10  
11  
12  
13  
OE  
A
0
21  
20  
19  
18  
17  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUT BUFFER  
A
13  
A
14  
CE  
I/O  
7
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
6
5
4
A
0
A
1
16  
15  
I/O  
I/O  
A
2
GND  
14  
3
A
3
A
4
32K x 8  
ARRAY  
A
5
A
6
A
7
A
8
A
9
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05467 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 10, 2005  
1234567...10

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