Datasheet > CY7C1380KV33

CY7C1380KV33

更新时间： 2024-11-28 00:58:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
33页	3208K
描述
18-Mbit (512K Ã 36/1M Ã 18) Pipelined SRAM

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CY7C1380KV33 数据手册

CY7C1380KV33

CY7C1382KV33

18-Mbit (512K × 36/1M × 18)

Pipelined SRAM

18-Mbit (512K

× 36/1M × 18) Pipelined SRAM

Features

Functional Description

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250, 200, and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 3.3 V core power supply

The CY7C1380KV33/CY7C1382KV33 SRAM integrates

524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive edge triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining chip enable (CE₁), depth-expansion

chip enables (CE₂and CE₃), burst control inputs (ADSC, ADSP,

and ADV), write enables (BW_X, and BWE), and global write

(GW). Asynchronous inputs include the output enable (OE) and

the ZZ pin.

■ 2.5 V or 3.3 V I/O power supply

■ Fast clock-to-output times

❐ 2.5 ns (for 250 MHz device)

■ Provides high performance 3-1-1-1 access rate

■ Separate processor and controller address strobes

■ Synchronous self-timed write

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP) or address strobe

controller (ADSC) are active. Subsequent burst addresses can

be internally generated as they are controlled by the advance pin

(ADV).

■ Asynchronous output enable

■ Single cycle chip deselect

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle. This part supports byte write

operations (see Pin Definitions on page 6 and Truth Table on

page 10 for further details). Write cycles can be one to two or four

bytes wide as controlled by the byte write control inputs. GW

when active LOW causes all bytes to be written.

■ Available in JEDEC-standard Pb-free 100-pin TQFP and non

Pb-free 165-ball FBGA package.

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ ZZ sleep mode option

The CY7C1380KV33/CY7C1382KV33 operates from a +3.3 V

core power supply while all outputs operate with a +2.5 or +3.3 V

power supply. All inputs and outputs are JEDEC-standard and

JESD8-5-compatible.

Selection Guide

Description

Maximum Access Time

250 MHz

2.5

200 MHz

3.0

167 MHz Unit

3.4

143

163

Maximum Operating Current

× 18

× 36

180

158

200

178

Cypress Semiconductor Corporation

Document Number: 001-97878 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 1, 2016

12 3 4 5 6 7...33

中文翻译

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与CY7C1380KV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1380KV33-167AXC	CYPRESS	获取价格	18-Mbit (512K Ã 36/1M Ã 18) Pipelined SRAM
CY7C1380KV33-167AXC	INFINEON	获取价格	Synchronous SRAM
CY7C1380KV33-167AXCT	INFINEON	获取价格	Synchronous SRAM
CY7C1380KV33-167AXI	CYPRESS	获取价格	Cache SRAM, 512KX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,
CY7C1380KV33-167AXI	INFINEON	获取价格	Synchronous SRAM
CY7C1380KV33-167AXIT	INFINEON	获取价格	Synchronous SRAM
CY7C1380KV33-167BZI	CYPRESS	获取价格	18-Mbit (512K Ã 36/1M Ã 18) Pipelined SRAM
CY7C1380KV33-200AXC	CYPRESS	获取价格	18-Mbit (512K Ã 36/1M Ã 18) Pipelined SRAM
CY7C1380KV33-250AXC	CYPRESS	获取价格	18-Mbit (512K Ã 36/1M Ã 18) Pipelined SRAM
CY7C138-15	CYPRESS	获取价格	4K x 8/9 Dual-Port Static RAM

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