Datasheet > 存储 > SRAM> CY7C1372BV25-133AC

CY7C1372BV25-133AC

更新时间： 2024-11-10 05:19:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
26页	726K
描述
512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

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技术参数
数据手册

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CY7C1372BV25-133AC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	针数：	100
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.76
Is Samacsys：	N	最长访问时间：	4.2 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	133 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	18874368 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	100
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
电源：	2.5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.02 A
最小待机电流：	2.38 V	子类别：	SRAMs
最大压摆率：	0.16 mA	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD (800)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

CY7C1372BV25-133AC 数据手册

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CY7C1372BV25

CY7C1370BV25

512K x 36/1M x 18 Pipelined SRAM

with NoBL™ Architecture

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂and CE₃), cycle start input (ADV/LD),

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b, BWS_c

and BWS_d), and Read-Write control (WE). BWS_cand BWS_d

apply to CY7C1370BV25 only.

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later, its associated data

occurs, either Read or Write.

Features

• Zero Bus Latency, no dead cycles between Write and

Read cycles

• Fast clock speed: 200,167, 150, and 133 MHz

• Fast access time: 3.0, 3.4, 3.8, 4.2 ns

• Internally synchronized registered outputs eliminate

the need to control OE

Clock Enable (CEN) pin allows operation of the

• Single 2.5V +5%

• Single WE (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

• Interleaved or linear 4-word burst capability

• Individual byte Write (BWS_a–BWS_d) control (may be

tied LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• JTAG boundary scan for BGA packaging version

CY7C1370BV25/CY7C1372BV25 to be suspended as long as

necessary. All synchronous inputs are ignored when (CEN) is

HIGH and the internal device registers will hold their previous

values.

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is LOW, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(Read or Write) will be completed. The data bus will be in

high-impedance state two cycles after chip is deselected or a

Write cycle is initiated.

• Available in 119-ball bump BGA and 100-pin TQFP

packages

The CY7C1370BV25 and CY7C1372BV25 have an on-chip

two-bit burst counter. In the burst mode, the CY7C1370BV25

and CY7C1372BV25 provide four cycles of data for a single

address presented to the SRAM. The order of the burst

sequence is defined by the MODE input pin. The MODE pin

selects between linear and interleaved burst sequence. The

ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH)

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

• Automatic power-down available using zz mode or CE

deselect

Functional Description

The CY7C1370BV25 and CY7C1372BV25 SRAMs are

designed to eliminate dead cycles when transitions from

READ to WRITE or vice versa. These SRAMs are optimized

for 100 percent bus utilization and achieves Zero Bus Latency.

They integrate 524,288 × 36 and 1,048,576 × 18 SRAM cells,

respectively, with advanced synchronous peripheral circuitry

and a 2-bit counter for internal burst operation. The Cypress

Synchronous Burst SRAM family employs high-speed,

low-power CMOS designs using advanced single layer

polysilicon, threelayer metal technology. Each memory cell

consists of six transistors.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

CEN

256K × 36/

512K × 18

MEMORY

ARRAY

CONTROL

and WRITE

LOGIC

CY7C1370 CY7C1372

X = 18:0 X = 19:0

BWS

Mode

X = a, b, c, d X = a, b

BWS

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05252 Rev. **

Revised April 8, 2002

12 3 4 5 6 7...26

中文翻译

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与CY7C1372BV25-133AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1372BV25-133AI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25-133BGC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25-133BGI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25-133BZC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25-133BZI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25-150AC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25-150AI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25-150BGC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25-150BGI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25-150BZC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

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