Datasheet > CY7C1363A

CY7C1363A

更新时间： 2024-11-16 05:19:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	818K
描述
256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM

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CY7C1363A 数据手册

CY7C1361A

CY7C1363A

256K x 36/512K x 18 Synchronous

Flow-Thru Burst SRAM

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), depth-expansion

Chip Enables (CE₂and CE₂), burst control inputs (ADSC,

ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and

BWE), and global Write (GW). However, the CE₂chip enable

input is only available for the TA package version.

Features

• Fast access times: 6.0, 6.5, 7.0, and 8.0ns

• Fast clock speed: 150, 133, 117, and 100MHz

• Fast OE access times: 3.5 ns and 4.0 ns

• Optimal for depth expansion (one cycle chip deselect

to eliminate bus contention)

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V_SSat all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Multiple chip enables for depth expansion: A package

version and two chip enables for BG and AJ package

versions

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data outputs (Q), enabled by

OE, are also asynchronous.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

• Address pipeline capability

• Address, data, and control registers

• Internally self-timed Write cycle

• Burst control pins (interleaved or linear burst

sequence)

• Automatic power-down feature available using ZZ

mode or CE deselect.

• JTAG boundary scan for BG and AJ package version

• Low-profile 119-bump 14-mm × 22-mm PBGA (Ball Grid

Array) and 100-pin TQFP packages

Address, data inputs, and Write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the Write control inputs.

Individual byte Write allows individual byte to be written. BWa

controls DQa. BWb controls DQb. BWc controls DQc. BWd

controls DQd. BWa, BWb, BWc, and BWd can be active only

with BWE being LOW. GW being LOW causes all bytes to be

written. The x18 version only has 18 data inputs/outputs (DQa

and DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

For the B and T package versions, four pins are used to

implement JTAG test capabilities: Test Mode Select (TMS),

Test Data-In (TDI), Test Clock (TCK), and Test Data-Out

(TDO). The JTAG circuitry is used to serially shift data to and

from the device. JTAG inputs use LVTTL/LVCMOS levels to

shift data during this testing mode of operation. The TA

package version does not offer the JTAG capability.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

triple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1361A and CY7C1363A operate from a +3.3V

power supply. All inputs and outputs are LVTTL-compatible.

The CY7C1361A and CY7C1363A SRAMs integrate 262,144

× 36 and 524,288 × 18 SRAM cells with advanced

Selection Guide

7C1361A-150

7C1363A-150

7C1361A-133

7C1363A-133

7C1361A-117

7C1363A-117

7C1361A-100

7C1363A-100

Unit

Maximum Access Time

6.0

480

6.5

360

7.0

320

8.0

270

Maximum Operating Current

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05259 Rev. *A

Revised June 19, 2002

12 3 4 5 6 7...26

中文翻译

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与CY7C1363A相关器件

型号	品牌	获取价格	描述	数据表
CY7C1363A-100AC	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
CY7C1363A-100AC	ROCHESTER	获取价格	512KX18 STANDARD SRAM, 9ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1363A-100ACT	CYPRESS	获取价格	Standard SRAM, 512KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1363A-100AI	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
CY7C1363A-100AIT	CYPRESS	获取价格	Standard SRAM, 512KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1363A-100AJC	ROCHESTER	获取价格	512KX18 STANDARD SRAM, 9ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1363A-100AJC	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
CY7C1363A-100AJCT	CYPRESS	获取价格	暂无描述
CY7C1363A-100AJI	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
CY7C1363A-100BGC	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM

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