Datasheet > CY7C1362B

CY7C1362B

更新时间： 2024-11-15 21:58:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
34页	859K
描述
9-Mbit (256K x 36/512K x 18) Pipelined SRAM

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CY7C1362B 数据手册

CY7C1360B

CY7C1362B

9-Mbit(256Kx36/512Kx18)PipelinedSRAM

Features

Functional Description^[1]

• Supports bus operation up to 225 MHz

• Available speed grades are 225, 200 and 166 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V/3.3V I/O operation

• Fast clock-to-output times

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

The CY7C1360B/CY7C1362B SRAM integrates 262,144 x 36

and 524,288 x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (

), depth-expansion Chip

CE₁

[2]

Enables (CE and

), Burst Control inputs (

CE₃

ADSC ADSP

), Write Enables (

ADV

, and

BW_X

), and Global Write

and

BWE

(

). Asynchronous inputs include the Output Enable (

)

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor ( ) or

• Provide high-performance 3-1-1-1 access rate

ADSP

) are active. Subsequent

Address Strobe Controller (

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

• User-selectable burst counter supporting Intel^

Pentium^®interleaved or linear burst sequences

ADV

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

• Single Cycle Chip Deselect

controlled by the Byte Write control inputs.

when active

causes all bytes to be written.

LOW

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA

and 165-Ball fBGA packages

The CY7C1360B/CY7C1362B operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Selection Guide

225 MHz

200 MHz

3.0

166 MHz

3.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

2.8

250

220

180

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for A version of TQFP (3 Chip Enable option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05291 Rev. *C

Revised April 9, 2004

12 3 4 5 6 7...34

中文翻译

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与CY7C1362B相关器件

型号	品牌	获取价格	描述	数据表
CY7C1362B-166AC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B-166AI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B-166AJC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B-166AJI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B-166BGC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B-166BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B-166BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B-200AC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B-200AI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B-200AJC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM

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