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CY7C1362A-200BGI PDF预览

CY7C1362A-200BGI

更新时间： 2024-09-28 05:19:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
28页 559K
描述
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

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CY7C1362A-200BGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, BGA-119
针数：119Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.81Is Samacsys：N
最长访问时间：3.1 ns其他特性：PIPELINE ARCHITECTURE
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：18
功能数量：1端子数量：119
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.4 mm最大待机电流：0.01 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.6 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

CY7C1362A-200BGI 数据手册

 浏览型号CY7C1362A-200BGI的Datasheet PDF文件第2页浏览型号CY7C1362A-200BGI的Datasheet PDF文件第3页浏览型号CY7C1362A-200BGI的Datasheet PDF文件第4页浏览型号CY7C1362A-200BGI的Datasheet PDF文件第5页浏览型号CY7C1362A-200BGI的Datasheet PDF文件第6页浏览型号CY7C1362A-200BGI的Datasheet PDF文件第7页 
CY7C1360A  
CY7C1362A  
256K x 36/512K x 18 Synchronous  
Pipelined Burst SRAM  
synchronous peripheral circuitry and a two-bit counter for  
internal burst operation. All synchronous inputs are gated by  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
inputs, address-pipelining Chip Enable (CE), depth-expansion  
Chip Enables (CE2 and CE3), burst control inputs (ADSC,  
ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and  
BWE), and global Write (GW). However, the CE3 chip enable  
input is only available for the TA package version.  
Features  
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Fast clock speed: 225, 200, 166, and 150 MHz  
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Optimal for depth expansion (one cycle chip deselect  
to eliminate bus contention)  
• 3.3V –5% and +10% power supply  
• 3.3V or 2.5V I/O supply  
• 5V-tolerant inputs except I/Os  
• Clamp diodes to VSS at all inputs and outputs  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
• Multiple chip enables for depth expansion:  
three chip enables for A package version and two chip  
enables for BG and AJ package versions  
Asynchronous inputs include the Output Enable (OE) and  
burst mode control (MODE). The data outputs (Q), enabled by  
OE, are also asynchronous.  
Addresses and chip enables are registered with either  
Address Status Processor (ADSP) or Address Status  
Controller (ADSC) input pins. Subsequent burst addresses  
can be internally generated as controlled by the Burst Advance  
Pin (ADV).  
• Address pipeline capability  
• Address, data, and control registers  
• Internally self-timed Write Cycle  
• Burst control pins (interleaved or linear burst  
sequence)  
• Automaticpower-downfeatureavailableusingZZmode  
or CE deselect  
• JTAG boundary scan for BG and AJ package version  
• Low-profile119-bump,14-mm×22-mmPBGA(BallGrid  
Array) and 100-pin TQFP packages  
Address, data inputs, and Write controls are registered on-chip  
to initiate self-timed Write cycle. Write cycles can be one to  
four bytes wide as controlled by the Write control inputs.  
Individual byte Write allows individual byte to be written. BWa  
controls DQa. BWb controls DQb. BWc controls DQc. BWd  
controls DQd. BWa, BWb, BWc, and BWd can be active only  
with BWE being LOW. GW being LOW causes all bytes to be  
written. The x18 version only has 18 data inputs/outputs (DQa  
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and  
DQd).  
For the B and T package versions, four pins are used to  
implement JTAG test capabilities: Test Mode Select (TMS),  
Test Data-In (TDI), Test Clock (TCK), and Test Data-Out  
(TDO). The JTAG circuitry is used to serially shift data to and  
from the device. JTAG inputs use LVTTL/LVCMOS levels to  
shift data during this testing mode of operation. The TA  
package version does not offer the JTAG capability.  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low-power CMOS designs using advanced  
triple-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high-valued  
resistors.  
The CY7C1360A and CY7C1362A operate from a +3.3V  
power supply. All inputs and outputs are LVTTL-compatible.  
The CY7C1360A and CY7C1362A SRAMs integrate 262,144  
×
36 and 524,288 × 18 SRAM cells with advanced  
Selection Guide  
7C1360A-225  
7C1362A-225  
7C1360A-200  
7C1362A-200  
7C1360A-166  
7C1362A-166  
7C1360A-150  
7C1362A-150  
Unit  
ns  
Maximum Access Time  
2.5  
650  
10  
3.0  
620  
10  
3.5  
530  
10  
3.5  
480  
10  
Maximum Operating Current  
Maximum CMOS Standby Current  
mA  
mA  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05258 Rev. *A  
Revised May 24, 2002  
1234567...28

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