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CY7C1357C-100BZI PDF预览

CY7C1357C-100BZI

更新时间： 2024-11-23 03:57:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
32页 483K
描述
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

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中文翻译

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CY7C1357C-100BZI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.65
最长访问时间：7.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：220电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.4 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.18 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

CY7C1357C-100BZI 数据手册

 浏览型号CY7C1357C-100BZI的Datasheet PDF文件第2页浏览型号CY7C1357C-100BZI的Datasheet PDF文件第3页浏览型号CY7C1357C-100BZI的Datasheet PDF文件第4页浏览型号CY7C1357C-100BZI的Datasheet PDF文件第5页浏览型号CY7C1357C-100BZI的Datasheet PDF文件第6页浏览型号CY7C1357C-100BZI的Datasheet PDF文件第7页 
CY7C1355C  
CY7C1357C  
PRELIMINARY  
9-Mbit (256K x 36/512K x 18) Flow-Through  
SRAM with NoBL™ Architecture  
Functional Description[1]  
Features  
• No Bus Latency™ (NoBL™) architecture eliminates  
The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/ 512K x 18  
Synchronous Flow-through Burst SRAM designed specifically  
to support unlimited true back-to-back Read/Write operations  
dead cycles between write and read cycles.  
• Can support up to 133-MHz bus operations with zero  
wait states  
— Data is transferred on every clock  
without  
the  
insertion  
of  
wait  
states.  
The  
CY7C1355C/CY7C1357C is equipped with the advanced No  
Bus Latency (NoBL) logic required to enable consecutive  
Read/Write operations with data being transferred on every  
clock cycle. This feature dramatically improves the throughput  
of data through the SRAM, especially in systems that require  
frequent Write-Read transitions.  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
Write operations are controlled by the two or four Byte Write  
Select (BWX) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
• Pin compatible and functionally equivalent to ZBT™  
devices  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Registered inputs for flow-through operation  
• Byte Write capability  
• 3.3V/2.5V I/O power supply  
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
— 7.0 ns (for 117-MHz device)  
— 7.5 ns (for 100-MHz device)  
• Clock Enable (CEN) pin to enable clock and suspend  
operation  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
• OfferedinJEDEC-standard100TQFP,119-BallBGAand  
165-Ball fBGA packages  
• Three chip enables for simple depth expansion.  
• Automatic Power-down feature available using ZZ  
mode or CE deselect  
• JTAG boundary scan for BGA and fBGA packages  
• Burst Capability—linear or interleaved burst order  
• Low standby power  
Selection Guide  
133 MHz  
117 MHz  
7.0  
100 MHz  
7.5  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
6.5  
250  
30  
220  
30  
180  
30  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05539 Rev. **  
Revised April 12, 2004  
1234567...32

中文翻译

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