CY7C1357C-117BGC

更新时间： 2024-11-19 03:57:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
32页	483K
描述
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

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CY7C1357C-117BGC 数据手册

CY7C1355C

CY7C1357C

PRELIMINARY

9-Mbit (256K x 36/512K x 18) Flow-Through

SRAM with NoBL™ Architecture

Functional Description^[1]

Features

• No Bus Latency™ (NoBL™) architecture eliminates

The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/ 512K x 18

Synchronous Flow-through Burst SRAM designed specifically

to support unlimited true back-to-back Read/Write operations

dead cycles between write and read cycles.

• Can support up to 133-MHz bus operations with zero

wait states

— Data is transferred on every clock

without

the

insertion

wait

states.

The

CY7C1355C/CY7C1357C is equipped with the advanced No

Bus Latency (NoBL) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of data through the SRAM, especially in systems that require

frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

Write operations are controlled by the two or four Byte Write

Select (BW_X) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 3.3V/2.5V I/O power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 7.0 ns (for 117-MHz device)

— 7.5 ns (for 100-MHz device)

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• OfferedinJEDEC-standard100TQFP,119-BallBGAand

165-Ball fBGA packages

• Three chip enables for simple depth expansion.

• Automatic Power-down feature available using ZZ

mode or CE deselect

• JTAG boundary scan for BGA and fBGA packages

• Burst Capability—linear or interleaved burst order

• Low standby power

Selection Guide

133 MHz

117 MHz

7.0

100 MHz

7.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

6.5

250

220

180

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05539 Rev. **

Revised April 12, 2004

12 3 4 5 6 7...32

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与CY7C1357C-117BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1357C-117BGI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1357C-117BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1357C-117BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1357C-133AC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1357C-133AI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1357C-133AXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRA
CY7C1357C-133AXCT	CYPRESS	获取价格	SRAM,
CY7C1357C-133AXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRA
CY7C1357C-133AXIT	CYPRESS	获取价格	ZBT SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, M
CY7C1357C-133BGC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

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