Datasheet > CY7C1358A-75AC

CY7C1358A-75AC

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
11页	146K
描述
Cache Tag SRAM, 64KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1358A-75AC 数据手册

327

CY7C1358A/

GVT7164T18

64K x 18 Synchronous Cache Tag RAM

Pipelined Output

Features

Functional Description

• Fast match times: 4.5, 5.0, 6.0, and 7.0 ns

• Fast clock speed: 133, 100, 83, and 75 MHz

• Fast OE access times: 4.5 ns and 5.0 ns

• Pipelined data comparator

• Data input register load control by DEN

• 3.3V –5% and +10% power supply

• 5V tolerant inputs except I/Os

The Cypress Synchronous SRAM family employs high-speed,

low-power CMOS designs using advanced triple-layer polysil-

icon, double-layer metal technology. Each memory cell con-

sists of four transistors and two high valued resistors.

The GVT7164T18 SRAM integrates 65,536 x 18 SRAM cells

with advanced synchronous peripheral circuitry and a 18-bit

comparator for tag compare operation. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

• Clamp diodes to V_SSat all inputs and outputs

• Common data inputs and data outputs

• Two chip enables for depth expansion

• Address, data, and control registers

• Internally self-timed Write cycle

Clock Input (CLK). The synchronous inputs include all ad-

dresses, all data inputs, depth-expansion Chip Enables (CE

and CE1), Write Enable (WE), and Data Input Enable (DEN).

Asynchronous inputs include the Output Enable (OE) and the

Match Output Enable (MOE). The Data Outputs (Q) and Match

Output (MATCH), enabled by OE and MOE respectively, are

also asynchronous.

• Automatic power-down for portable applications

• Low profile 100-pin TQFP package

Data inputs are registered with Data Input Enable (DEN) and

Chip Enable pins (CE, CE1). The outputs of the data input

registers are compared with data in the memory array and a

match signal is generated. The match output is gated into a

pipeline register and released to the match output pin at the

next rising edge of Clock (CLK).

The GVT7164T18 operates from a +3.3V power supply. All

inputs and outputs are LVTTL compatible. The device is ideally

suited for address tag RAM for up to 2 MB secondary cache.

Selection Guide

7C1358A-133

7164T18-4

7C1358A-100

7164T18-5

7C1358A-83

7164T18-6

7C1358A-75

7164T18-7

Maximum Access Time (ns)

4.5

300

5.0

240

6.0

220

7.0

200

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Cypress Semiconductor Corporation

Document #: 38-05121 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised January 19, 2003

12 3 4 5 6 7...11

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