Datasheet > CY7C1338B

CY7C1338B

更新时间： 2024-11-28 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	600K
描述
128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

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中文翻译

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数据手册

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CY7C1338B 数据手册

338B

CY7C1338B

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Features

Functional Description

• Supports117-MHzmicroprocessorcachesystemswith

The CY7C1338B is a 3.3V, 128K by 32 synchronous cache

RAM designed to interface with high-speed microprocessors

with minimum glue logic. Maximum access delay from clock

rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-

tures the first address in a burst and increments the address

automatically for the rest of the burst access.

zero wait states

• 128K by 32 common I/O

• Fast clock-to-output times

— 7.5 ns (117-MHz version)

• Two-bit wraparound counter supporting either inter-

leaved or linear burst sequence

• Separate processor and controller address strobes

providedirectinterfacewiththeprocessorandexternal

cache controller

• Synchronous self-timed write

• Asynchronous output enable

• 3.3V/ 2.5V I/Os

• JEDEC-standard pinout

• 100-pin TQFP packaging

• ZZ “sleep” mode

The CY7C1338B allows both interleaved and linear burst se-

quences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses can be initiated with the Processor

Address Strobe (ADSP) or the cache Controller Address

Strobe (ADSC) inputs. Address advancement is controlled by

the Address Advancement (ADV) input.

A synchronous self-timed write mechanism is provided to sim-

plify the write interface. A synchronous chip enable input and

an asynchronous output enable input provide easy control for

bank selection and output three-state control.

• Available in Commercial and Industrial Temperatures

Logic Block Diagram

MODE

(A₀,A₁)

CLK

ADV

ADSC

BURST

COUNTER

CLR

ADSP

ADDRESS

128K X 32

MEMORY

ARRAY

A_[16:0]

DQ[31:24]

BYTEWRITE

REGISTERS

BWE

DQ[23:16]

BYTEWRITE

REGISTERS

DQ[15:8]

BYTEWRITE

REGISTERS

DQ[7:0]

BYTEWRITE

REGISTERS

ENABLE

CLK

INPUT

REGISTERS

CLK

SLEEP

CONTROL

DQ_[31:0]

Selection Guide

-117

7.5

-100

Maximum Access Time (ns)

8.0

325

2.0

Maximum Operating Current (mA)

350

2.0

Maximum Standby Current (mA)

Pentium is a registered trademark of Intel Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05143 Rev. **

Revised September 6, 2001

12 3 4 5 6 7...18

中文翻译

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与CY7C1338B相关器件

型号	品牌	获取价格	描述	数据表
CY7C1338B-100AC	ROCHESTER	获取价格	128KX32 CACHE SRAM, 8ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1338B-100AC	CYPRESS	获取价格	128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
CY7C1338B-100ACT	CYPRESS	获取价格	Cache SRAM, 128KX32, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1338B-100AI	CYPRESS	获取价格	128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
CY7C1338B-100AI	ROCHESTER	获取价格	128KX32 CACHE SRAM, 8ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1338B-100AIT	CYPRESS	获取价格	Cache SRAM, 128KX32, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1338B-100BGC	CYPRESS	获取价格	128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
CY7C1338B-100BGC	ROCHESTER	获取价格	128KX32 CACHE SRAM, 8ns, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1338B-100BGCT	ROCHESTER	获取价格	128KX32 CACHE SRAM, 8ns, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1338B-100BGI	CYPRESS	获取价格	128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

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