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CY7C1338B-100ACT PDF预览

CY7C1338B-100ACT

更新时间: 2024-11-23 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
18页 600K
描述
Cache SRAM, 128KX32, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

CY7C1338B-100ACT 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.75
最长访问时间:8 ns其他特性:FLOW-THROUGH ARCHITECTURE
JESD-30 代码:R-PQFP-G100长度:20 mm
内存密度:4194304 bit内存集成电路类型:CACHE SRAM
内存宽度:32功能数量:1
端子数量:100字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX32封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

CY7C1338B-100ACT 数据手册

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338B  
CY7C1338B  
128K x 32 Synchronous-Flow-Through 3.3V Cache RAM  
Features  
Functional Description  
• Supports117-MHzmicroprocessorcachesystemswith  
The CY7C1338B is a 3.3V, 128K by 32 synchronous cache  
RAM designed to interface with high-speed microprocessors  
with minimum glue logic. Maximum access delay from clock  
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-  
tures the first address in a burst and increments the address  
automatically for the rest of the burst access.  
zero wait states  
• 128K by 32 common I/O  
• Fast clock-to-output times  
— 7.5 ns (117-MHz version)  
• Two-bit wraparound counter supporting either inter-  
leaved or linear burst sequence  
• Separate processor and controller address strobes  
providedirectinterfacewiththeprocessorandexternal  
cache controller  
• Synchronous self-timed write  
• Asynchronous output enable  
• 3.3V/ 2.5V I/Os  
• JEDEC-standard pinout  
• 100-pin TQFP packaging  
• ZZ “sleep” mode  
The CY7C1338B allows both interleaved and linear burst se-  
quences, selected by the MODE input pin. A HIGH selects an  
interleaved burst sequence, while a LOW selects a linear burst  
sequence. Burst accesses can be initiated with the Processor  
Address Strobe (ADSP) or the cache Controller Address  
Strobe (ADSC) inputs. Address advancement is controlled by  
the Address Advancement (ADV) input.  
A synchronous self-timed write mechanism is provided to sim-  
plify the write interface. A synchronous chip enable input and  
an asynchronous output enable input provide easy control for  
bank selection and output three-state control.  
• Available in Commercial and Industrial Temperatures  
Logic Block Diagram  
MODE  
(A0,A1)  
2
Q
Q
CLK  
ADV  
ADSC  
0
BURST  
COUNTER  
CE  
CLR  
1
ADSP  
Q
15  
17  
ADDRESS  
REGISTER  
CE  
D
128K X 32  
MEMORY  
ARRAY  
A[16:0]  
GW  
17  
15  
Q
Q
Q
Q
DQ[31:24]  
D
BYTEWRITE  
REGISTERS  
BWE  
BW  
3
D
D
D
DQ[23:16]  
BYTEWRITE  
REGISTERS  
BW  
2
DQ[15:8]  
BYTEWRITE  
REGISTERS  
BW  
1
DQ[7:0]  
BW  
0
BYTEWRITE  
REGISTERS  
32  
32  
CE  
1
CE  
2
D
CE  
ENABLE  
REGISTER  
CLK  
Q
CE  
3
INPUT  
REGISTERS  
CLK  
OE  
ZZ  
SLEEP  
CONTROL  
DQ[31:0]  
Selection Guide  
-117  
7.5  
-100  
Maximum Access Time (ns)  
8.0  
325  
2.0  
Maximum Operating Current (mA)  
350  
2.0  
Maximum Standby Current (mA)  
Pentium is a registered trademark of Intel Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05143 Rev. **  
Revised September 6, 2001  

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