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CY7C1338F

更新时间: 2024-11-22 22:02:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
17页 405K
描述
4-Mb (128K x 32) Flow-Through Sync SRAM

CY7C1338F 数据手册

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CY7C1338F  
4-Mb (128K x 32) Flow-Through Sync SRAM  
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the  
first address in a burst and increments the address automati-  
cally for the rest of the burst access. All synchronous inputs  
Features  
• 128K X 32 common I/O  
• 3.3V –5% and +10% core power supply (VDD  
are gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
)
• 2.5V or 3.3V I/O supply (VDDQ  
• Fast clock-to-output times  
— 6.5 ns (133-MHz version)  
— 7.5 ns (117-MHz version)  
— 8.0 ns (100-MHz version)  
— 11.0 ns (66-MHz version)  
)
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
CE1  
2
Control inputs (  
,
,
), Write Enables  
). Asynchronous  
and  
ADV  
ADSC ADSP  
(
,
and  
), and Global Write (  
BW[A:D]  
BWE  
GW  
(
)
and the ZZ pin  
.
nputs include the Output Enable  
OE  
i
The CY7C1338F allows either interleaved or linear burst  
sequences, selected by the MODE input pin. A HIGH selects  
an interleaved burst sequence, while a LOW selects a linear  
burst sequence. Burst accesses can be initiated with the  
Processor Address Strobe (ADSP) or the cache Controller  
Address Strobe (ADSC) inputs. Address advancement is  
controlled by the Address Advancement (ADV) input.  
• Provide high-performance 2-1-1-1 access rate  
User-selectable burst counter supporting Intel  
Pentiuminterleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
Addresses and chip enables are registered at rising edge of  
• Asynchronous output enable  
clock when either Address Strobe Processor (  
) or  
ADSP  
• Offered in JEDEC-standard 100-pin TQFP and 119-ball  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
BGA packages  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
• “ZZ” Sleep Mode option  
ADV  
Functional Description[1]  
The CY7C1338F is a 131,072 x 32 synchronous cache RAM  
designed to interface with high-speed microprocessors with  
minimum glue logic. Maximum access delay from clock rise is  
The CY7C1338F operates from a +3.3V core power supply  
while all outputs may operate with either a +2.5 or +3.3V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Logic Block Diagram  
ADDRESS  
REGISTER  
A0, A1, A  
A[1:0]  
MODE  
ADV  
CLK  
Q1  
BURST  
COUNTER  
AND LOGIC  
Q0  
CLR  
ADSC  
ADSP  
DQ  
D BYTE  
DQ  
D BYTE  
WRITE REGISTER  
BW  
D
WRITE REGISTER  
DQ  
C BYTE  
DQ  
C BYTE  
WRITE REGISTER  
BW  
C
WRITE REGISTER  
OUTPUT  
BUFFERS  
MEMORY  
ARRAY  
SENSE  
AMPS  
DQs  
DQ  
B BYTE  
DQ  
B BYTE  
WRITE REGISTER  
BW  
B
WRITE REGISTER  
DQ  
A BYTE  
WRITE REGISTER  
DQA BYTE  
BW  
A
WRITE REGISTER  
BWE  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
CE1  
CE2  
CE3  
OE  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-05218 Rev. *A  
Revised February 2, 2004  

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