CY7C1328F-225AXI

更新时间： 2024-11-29 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
17页	342K
描述
暂无描述

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1328F-225AXI 数据手册

CY7C1328F

4-Mb(256Kx18)PipelinedDCDSyncSRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

• 256K × 18-bit common I/O architecture

• 3.3V –5% and +10% core power supply (V_DD

)

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

• 3.3V / 2.5V I/O supply (V_DDQ

)

Control inputs (

), Write Enables

). Asynchronous

and

ADV

ADSC ADSP

(

, and

BW_[A:B]

), and Global Write (

BWE GW

• Fast clock-to-output times

inputs include the Output Enable ( ) and the ZZ pin.

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^

controlled by the byte write control inputs.

active

LOW

Pentium^interleaved or linear burst sequences

This device incorporates an

causes all bytes to be written.

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100-pin TQFP package and pinout

• “ZZ” Sleep Mode option

The CY7C1328F operates from a +3.3V core power supply

while all outputs operate with a +3.3V or a +2.5V supply. All

inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

250 MHz

2.6

225 MHz

2.6

200 MHz

2.8

166 MHz

3.5

133 MHz

4.0

100 MHz

4.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

325

290

265

240

225

205

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05220 Rev. *A

Revised January 19, 2004

12 3 4 5 6 7...17

中文翻译

下载PDF

与CY7C1328F-225AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1328F-250AC	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined DCD Sync SRAM
CY7C1328F-250AI	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined DCD Sync SRAM
CY7C1328F-250AXC	CYPRESS	获取价格	暂无描述
CY7C1328F-250AXI	CYPRESS	获取价格	Cache SRAM, 256KX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1328G	CYPRESS	获取价格	4-Mbit (256K x 18) Pipelined DCD Sync SRAM
CY7C1328G_12	CYPRESS	获取价格	4-Mbit (256 K Ã 18) Pipelined DCD Sync SRAM
CY7C1328G_13	CYPRESS	获取价格	4-Mbit (256 K x 18) Pipelined DCD Sync SRAM
CY7C1328G-133AXC	CYPRESS	获取价格	4-Mbit (256K x 18) Pipelined DCD Sync SRAM
CY7C1328G-133AXI	CYPRESS	获取价格	4-Mbit (256K x 18) Pipelined DCD Sync SRAM
CY7C1328G-133AXIT	CYPRESS	获取价格	Standard SRAM, 256KX18, 4ns, CMOS, PQFP100,

与CY7C1328F-225AXI相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

49
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

38
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

67
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

62

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1328F-225AXI

CY7C1328F-225AXI 数据手册

与CY7C1328F-225AXI相关器件

与CY7C1328F-225AXI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1328F-225AXI

CY7C1328F-225AXI 数据手册

与CY7C1328F-225AXI相关器件

与CY7C1328F-225AXI相关文章

您还可以找

您在本页遇到什么问题？