Datasheet > 存储 > SRAM> CY7C1328G-200AXI

CY7C1328G-200AXI

更新时间： 2024-11-29 02:56:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
16页	377K
描述
4-Mbit (256K x 18) Pipelined DCD Sync SRAM

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CY7C1328G-200AXI 数据手册

CY7C1328G

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

The CY7C1328G SRAM integrates 256K x 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

• 256K × 18 common I/O architecture

• 3.3V core power supply (V_DD

)

• 3.3V/2.5V I/O power supply (V_DDQ

)

Control inputs (ADSC, ADSP,

(BW_[A:B], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

ADV), Write Enables

and

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

controlled by the byte write control inputs. GW active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• Asynchronous Output Enable

• Available in lead-free 100-Pin TQFP package

• “ZZ” Sleep Mode option

The CY7C1328G operates from a +3.3V core power supply

while all outputs operate with a +3.3V or a +2.5V supply. All

inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

2.8

167 MHz

3.5

133 MHz

4.0

Unit

Maximum Access Time

2.6

325

Maximum Operating Current

Maximum CMOS Standby Current

265

240

225

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05523 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 5, 2006

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与CY7C1328G-200AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1328G-250AXC	CYPRESS	获取价格	4-Mbit (256K x 18) Pipelined DCD Sync SRAM
CY7C1328G-250AXI	CYPRESS	获取价格	4-Mbit (256K x 18) Pipelined DCD Sync SRAM
CY7C1329	CYPRESS	获取价格	64K x 32 Synchronous-Pipelined Cache RAM
CY7C1329_04	CYPRESS	获取价格	64K x 32 Synchronous-Pipelined Cache RAM
CY7C1329-100AC	CYPRESS	获取价格	64K x 32 Synchronous-Pipelined Cache RAM
CY7C1329-100ACT	CYPRESS	获取价格	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1329-100AI	CYPRESS	获取价格	64K x 32 Synchronous-Pipelined Cache RAM
CY7C1329-100AXC	CYPRESS	获取价格	暂无描述
CY7C1329-100AXCT	CYPRESS	获取价格	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1329-133AC	CYPRESS	获取价格	64K x 32 Synchronous-Pipelined Cache RAM

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