Datasheet > CY7C1325H

CY7C1325H

更新时间： 2024-11-19 12:52:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
21页	731K
描述
4-Mbit (256 K Ã 18) Flow-Through Sync SRAM

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中文翻译

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CY7C1325H 数据手册

CY7C1325H

4-Mbit (256 K × 18) Flow-Through

Sync SRAM

4-Mbit (256

K × 18) Flow-Through Sync SRAM

Features

Functional Description

■ 256 K × 18 common I/O

The CY7C1325H is a 256 K × 18 synchronous cache RAM

designed to interface with high speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133 MHz version). A 2 bit on-chip counter captures the

first address in a burst and increments the address automatically

for the rest of the burst access. All synchronous inputs are gated

by registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining chip enable (CE₁), depth-expansion

chip enables (CE₂and CE₃), burst control inputs (ADSC, ADSP,

and ADV), write enables (BW_[A:B], and BWE), and global write

(GW). Asynchronous inputs include the output enable (OE) and

the ZZ pin.

■ 3.3 V core power supply (V_DD

)

■ 2.5 V or 3.3 V I/O power supply (V_DDQ

)

■ Fast clock-to-output times

■ 6.5 ns (133 MHz version)

■ Provide high performance 2-1-1-1 access rate

■ User selectable burst counter supporting Intel Pentium

interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self timed write

The CY7C1325H allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses can be initiated with the processor

address strobe (ADSP) or the cache controller address strobe

(ADSC) inputs.

■ Asynchronous output enable

■ Available in Pb-free 100-pin TQFP package

■ “ZZ” sleep mode option

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

The CY7C1325H operates from a +3.3 V core power supply

while all outputs may operate with either a +2.5 or +3.3 V supply.

All

inputs

and

outputs

are

JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram

ADDRESS

A0,A1,A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSC

ADSP

B,DQP B

WRITE DRIVER

WRITE REGISTER

MEMORY

ARRAY

OUTPUT

BUFFERS

DQs

DQP

SENSE

AMPS

DQ A,DQP A

WRITE DRIVER

DQ A,DQP A

WRITE REGISTER

BWE

INPUT

REGISTERS

ENABLE

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document Number: 001-86114 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 20, 2013

12 3 4 5 6 7...21

中文翻译

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与CY7C1325H相关器件

型号	品牌	获取价格	描述	数据表
CY7C1325H-133AXI	CYPRESS	获取价格	4-Mbit (256 K Ã 18) Flow-Through Sync SRAM
CY7C1325L-80AC	CYPRESS	获取价格	Cache SRAM, 256KX18, 8.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C1326F	CYPRESS	获取价格	2-Mb (128K x 18) Pipelined Sync SRAM
CY7C1326F-100AC	CYPRESS	获取价格	2-Mb (128K x 18) Pipelined Sync SRAM
CY7C1326F-100ACT	CYPRESS	获取价格	Cache SRAM, 128KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1326F-100AXC	CYPRESS	获取价格	Cache SRAM, 128KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1326H	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326H-133AXC	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326H-133AXI	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326H-166AXC	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM

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