Datasheet > CY7C1326F

CY7C1326F

更新时间： 2024-11-19 05:19:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	332K
描述
2-Mb (128K x 18) Pipelined Sync SRAM

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中文翻译

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CY7C1326F 数据手册

CY7C1326F

2-Mb (128K x 18) Pipelined Sync SRAM

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Features

• Registered inputs and outputs for pipelined operation

• 128K × 18 common I/O architecture

• 3.3V core power supply

• 3.3V I/O operation

• Fast clock-to-output times

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

Control inputs (

and

), Write Enables

ADV

ADSC ADSP

(

and ), and Global Write (

BWE

). Asynchronous

BW_[A:B]

inputs include the Output Enable ( ) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

• Provide high-performance 3-1-1-1 access rate

ADV

• User-selectable burst counter supporting Intel^

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP package

• “ZZ” Sleep Mode Option

Functional Description^[1]

controlled by the Byte Write control inputs.

when active

causes all bytes to be written.

LOW

The CY7C1326F operates from a +3.3V core power supply

while all outputs also operate with a +3.3V supply. All inputs

and outputs are JEDEC-standard JESD8-5-compatible.

The CY7C1326F SRAM integrates 131,072 x18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

Logic Block Diagram

ADDRESS

A0, A1, A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

ADSC

ADSP

DQB,DQPB

WRITE REGISTER

WRITE DRIVER

OUTPUT

BUFFERS

BWB

DQs

DQP

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY

DQA,DQPA

WRITE REGISTER

WRITE DRIVER

BWA

BWE

INPUT

REGISTERS

ENABLE

CE1

CE2

PIPELINED

ENABLE

CE3

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05424 Rev. **

Revised January 25, 2004

12 3 4 5 6 7...15

中文翻译

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与CY7C1326F相关器件

型号	品牌	获取价格	描述	数据表
CY7C1326F-100AC	CYPRESS	获取价格	2-Mb (128K x 18) Pipelined Sync SRAM
CY7C1326F-100ACT	CYPRESS	获取价格	Cache SRAM, 128KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1326F-100AXC	CYPRESS	获取价格	Cache SRAM, 128KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1326H	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326H-133AXC	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326H-133AXI	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326H-166AXC	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326H-166AXI	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326L-117AC	CYPRESS	获取价格	Cache SRAM, 128KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1327A-133AC	ROCHESTER	获取价格	256KX18 STANDARD SRAM, 4ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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