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CY7C1327A-150BGC PDF预览

CY7C1327A-150BGC

更新时间: 2024-11-19 14:48:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
16页 279K
描述
Standard SRAM, 256KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

CY7C1327A-150BGC 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数:119Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.83Is Samacsys:N
最长访问时间:3.8 ns其他特性:PIPELINE ARCHITECTURE
最大时钟频率 (fCLK):150 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:4718592 bit
内存集成电路类型:STANDARD SRAM内存宽度:18
功能数量:1端子数量:119
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA119,7X17,50
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL电源:2.5/3.3,3.3 V
认证状态:Not Qualified座面最大高度:2.4 mm
最大待机电流:0.01 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.4 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:14 mmBase Number Matches:1

CY7C1327A-150BGC 数据手册

 浏览型号CY7C1327A-150BGC的Datasheet PDF文件第2页浏览型号CY7C1327A-150BGC的Datasheet PDF文件第3页浏览型号CY7C1327A-150BGC的Datasheet PDF文件第4页浏览型号CY7C1327A-150BGC的Datasheet PDF文件第5页浏览型号CY7C1327A-150BGC的Datasheet PDF文件第6页浏览型号CY7C1327A-150BGC的Datasheet PDF文件第7页 
327A  
CY7C1327A/GVT71256G18  
256K x 18 Synchronous Pipelined Burst SRAM  
eral circuitry and a 2-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a pos-  
Features  
• Fast access times: 3.5, 3.8, and 4.0 ns  
itive-edge-triggered Clock Input (CLK). The synchronous in-  
puts include all addresses, all data inputs, address-pipelining  
Chip Enable (CE), depth-expansion Chip Enables (CE2 and  
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write  
Enables (WEL, WEH, and BWE), and Global Write (GW).  
• Fast clock speed: 166, 150, 133, and 117 MHz  
• Provide high-performance 3-1-1-1 access rate  
• Fast OE access times: 3.5 ns and 3.8 ns  
• Optimal for depth expansion (one cycle chip deselect  
to eliminate bus contention)  
• 3.3V –5% and +10% power supply  
• 2.5V or 3.3V I/O supply  
• 5V tolerant inputs except I/Os  
• Clamp diodes to VSSQ at all inputs and outputs  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
• Three chip enables for depth expansion and address  
pipeline  
• Address, data and control registers  
• Internally self-timed Write Cycle  
• Burst control pins (interleaved or linear burst se-  
quence)  
Asynchronous inputs include the Output Enable (OE) and  
Burst Mode Control (MODE). The data outputs (Q), enabled  
by OE, are also asynchronous.  
Addresses and chip enables are registered with either Ad-  
dress Status Processor (ADSP) or Address Status Controller  
(ADSC) input pins. Subsequent burst addresses can be inter-  
nally generated as controlled by the Burst Advance pin (ADV).  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle. Write cycles can be one to  
four bytes wide as controlled by the write control inputs. Indi-  
vidual byte write allows individual byte to be written. WEL con-  
trols DQ1DQ8 and DQP1. WEH controls DQ9DQ16 and  
DQP2. WEL and WEH can be active only with BWE being  
LOW. GW being LOW causes all bytes to be written. Write  
pass-through capability allows written data available at the  
output for the immediately next Read cycle. This device also  
incorporates pipelined enable circuit for easy depth expansion  
without penalizing system performance.  
• Automatic power-down for portable applications  
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid  
Array) and 100-pin TQFP packages  
The CY7C1327A/GVT71256G18 operates from a +3.3V pow-  
er supply and all outputs operate on a +2.5V supply. All inputs  
and outputs are JEDEC standard JESD8-5 compatible. The  
device is ideally suited for 486, Pentium®, 680x0, and Power-  
PCsystems and for systems that benefit from a wide syn-  
chronous data bus.  
Functional Description  
The Cypress Synchronous Burst SRAM family employs high-  
speed, low-power CMOS designs using advanced triple-layer  
polysilicon, double-layer metal technology. Each memory cell  
consists of four transistors and two high-valued resistors.  
The  
CY7C1327A/GVT71256G18  
SRAM  
integrates  
262,144x18 SRAM cells with advanced synchronous periph-  
Selection Guide  
7C1327A-166  
71256G18-3  
7C1327A-150  
71256G18-4  
7C1327A-133  
71256G18-5  
7C1327A-117  
71256G18-6  
Maximum Access Time (ns)  
3.5  
425  
10  
3.8  
400  
10  
4.0  
375  
10  
4.0  
350  
10  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Cypress Semiconductor Corporation  
Document #: 38-05129 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised November 13, 2002  

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