Datasheet > CY7C1326H-133AXC

CY7C1326H-133AXC

更新时间： 2024-11-19 02:56:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	675K
描述
2-Mbit (128K x 18) Pipelined Sync SRAM

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CY7C1326H-133AXC 数据手册

CY7C1326H

2-Mbit (128K x 18) Pipelined Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• 128K × 18 common I/O architecture

• 3.3V core power supply

The CY7C1326H SRAM integrates 128K x 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

• 3.3V/2.5V I/O operation

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

Control inputs (ADSC, ADSP,

(BW_[A:B]and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

ADV), Write Enables

and

— 4.0 ns (for 133-MHz device)

• Provide high-performance 3-1-1-1 access rate

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

controlled by the Byte Write control inputs. GW when active

• Asynchronous output enable

• Offered in JEDEC-standard lead-free 100-pin TQFP

package

• “ZZ” Sleep Mode Option

causes all bytes to be written.

LOW

The CY7C1326H operates from a +3.3V core power supply

while all outputs also operate with either a +3.3V/2.5V supply.

All

inputs

and

outputs

are

JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram

ADDRESS

A0, A1, A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

ADSC

ADSP

DQB,DQPB

WRITE REGISTER

WRITE DRIVER

OUTPUT

BUFFERS

BWB

DQs

DQP

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY

DQA,DQPA

WRITE REGISTER

WRITE DRIVER

BWA

BWE

INPUT

REGISTERS

ENABLE

CE1

CE2

PIPELINED

ENABLE

CE3

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05675 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 6, 2006

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与CY7C1326H-133AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1326H-133AXI	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326H-166AXC	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326H-166AXI	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined Sync SRAM
CY7C1326L-117AC	CYPRESS	获取价格	Cache SRAM, 128KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1327A-133AC	ROCHESTER	获取价格	256KX18 STANDARD SRAM, 4ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1327A-133BGC	CYPRESS	获取价格	Standard SRAM, 256KX18, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1327A-150AC	CYPRESS	获取价格	Standard SRAM, 256KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
CY7C1327A-150BGC	CYPRESS	获取价格	Standard SRAM, 256KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1327A-166BGC	CYPRESS	获取价格	Standard SRAM, 256KX18, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1327B	CYPRESS	获取价格	256K x 18 Synchronous-Pipelined Cache RAM

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