CY7C1325G
4-Mbit (256 K × 18) Flow through Sync
SRAM
4-Mbit (256
K × 18) Flow through Sync SRAM
Features
Functional Description
■ 256 K × 18 common I/O
The CY7C1325G[1] is a 256 K × 18 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A 2 bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
■ 3.3 V core power supply (VDD
)
■ 2.5 V or 3.3 V I/O power supply (VDDQ
)
■ Fast clock-to-output times
■ 6.5 ns (133 MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
and ADV), write enables (BW[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
■ Separate processor and controller address strobes
■ Synchronous self timed write
The CY7C1325G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package, Pb-free and non
Pb-free 119-ball BGA Package
■ “ZZ” sleep mode option
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1325G operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
.
Logic Block Diagram
ADDRESS
REGISTER
A0,A1,A
A[1:0]
Q1
MODE
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQP B
DQ
B,DQP B
WRITE DRIVER
WRITE REGISTER
BW
B
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQP A
DQ A,DQP A
WRITE REGISTER
WRITE DRIVER
BW
A
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
1
2
3
CE
OE
SLEEP
CONTROL
ZZ
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05518 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 29, 2011
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