Datasheet > 存储 > SRAM> CY7C1325G-100BGI

CY7C1325G-100BGI

更新时间： 2024-01-27 12:09:52

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
16页	364K
描述
4-Mbit (256K x 18) Flow-Through Sync SRAM

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CY7C1325G-100BGI 数据手册

CY7C1325G

4-Mbit (256K x 18) Flow-Through Sync SRAM

Features

Functional Description^[1]

• 256K x 18 common I/O

The CY7C1325G is a 256 K x 18 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

• 3.3V core power supply (V_DD

)

• 2.5V or 3.3V I/O power supply (V_DDQ

)

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW_[A:B], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

The CY7C1325G allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs.

• Asynchronous output enable

• Available in lead-free 100-Pin TQFP package, lead-free

and non-lead-free 119-Ball BGA package

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1325G operates from a +3.3V core power supply

while all outputs may operate with either a +2.5 or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram

ADDRESS

A0,A1,A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSC

ADSP

B,DQPB

WRITE DRIVER

WRITE REGISTER

MEMORY

ARRAY

OUTPUT

BUFFERS

DQs

DQP

SENSE

AMPS

A,DQPA

DQA,DQPA

WRITE REGISTER

WRITE DRIVER

BWE

INPUT

REGISTERS

ENABLE

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05518 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 4, 2006

12 3 4 5 6 7...16

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与CY7C1325G-100BGI相关器件

型号	品牌	描述	获取价格	数据表
CY7C1325G-100BGXC	CYPRESS	4-Mbit (256K x 18) Flow-Through Sync SRAM	获取价格
CY7C1325G-100BGXCT	CYPRESS	Cache SRAM, 256KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119	获取价格
CY7C1325G-100BGXI	CYPRESS	4-Mbit (256K x 18) Flow-Through Sync SRAM	获取价格
CY7C1325G-117AXC	CYPRESS	4-Mbit (256K x 18) Flow-Through Sync SRAM	获取价格
CY7C1325G-117AXI	CYPRESS	4-Mbit (256K x 18) Flow-Through Sync SRAM	获取价格
CY7C1325G-117BGC	CYPRESS	4-Mbit (256K x 18) Flow-Through Sync SRAM	获取价格

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