CY7C1325B
I/Os must be three-stated prior to the presentation of data to
DQ and DP . As a safety precaution, the data lines are
three-stated once a write cycle is detected, regardless of the
state of OE.
Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor’s Sequence
[15:0]
[1:0]
First
Second
Address
Third
Address
Fourth
Address
Address
Single Write Accesses Initiated by ADSC
A
,A
A
, A
A
, A
A
, A
X + 1 x
This write access is initiated when the following conditions are
X + 1
x
X + 1
x
X + 1
x
satisfied at clock rise: (1) CE , CE , and CE are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
1
2
3
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
HIGH, and (4) the write input signals (GW, BWE, and BWS
)
[1:0]
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register,
burst counter/control logic and delivered to the RAM core. The
information presented to DQ
and DP
will be written
[15:0]
[1:0]
Table 2. Counter Implementation for a Linear Sequence
into the specified address location. Byte writes are allowed,
with BWS controlling DQ and DP while BWS controlling
0
[7:0]
0
1
First
Address
Second
Address
Third
Address
Fourth
Address
DQ
and DP . All I/Os are three-stated when a write is
[15:8]
1
detected, even a byte write. Since these are common I/O de-
vices, the asynchronous OE input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
A
, A
A
, A
A
, A
A
, A
X + 1 x
X + 1
x
X + 1
x
X + 1
x
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
data to DQ
and DP
. As a safety precaution, the data
[15:0]
[1:0]
lines are three-stated once a write cycle is detected, regard-
less of the state of OE.
Burst Sequences
This family of devices provides a 2-bit wrap-around burst
Sleep Mode
counter inside the SRAM. The burst counter is fed by A
,
[1:0]
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to an interleaved
burst sequence.
“sleep” mode. CE , CE , CE , ADSP, and ADSC must remain
1
2
3
inactive for the duration of t
LOW.
after the ZZ input returns
ZZREC
5
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