CY7C1325B
Pin Configurations (continued)
119-Ball BGA
2
1
3
A
A
A
4
5
A
A
A
6
A
7
V
A
CE
A
ADSP
ADSC
V
DDQ
A
B
C
D
E
F
DDQ
NC
NC
DQ
CE
A
NC
NC
NC
DQ
2
3
V
DD
NC
DQ
V
NC
V
DQP
NC
b
SS
SS
SS
SS
SS
SS
a
NC
V
V
CE
V
V
b
1
a
V
NC
DQ
OE
ADV
GW
DQ
V
DDQ
DDQ
a
NC
BW
V
NC
DQ
G
H
J
b
b
ss
a
DQ
NC
V
V
DQ
V
NC
b
SS
SS
a
V
V
NC
V
NC
V
DDQ
DDQ
DD
DD
DD
NC
DQ
DQ
V
CLK
V
NC
DQ
K
b
SS
SS
a
NC
DQ
V
NC
BWE
A1
BW
DQ
NC
L
M
N
b
ss
a
a
V
V
V
V
NC
V
DDQ
DDQ
b
SS
SS
SS
DQ
NC
V
DQ
a
NC
b
SS
NC
DQP
A
V
A0
V
V
NC
A
DQ
P
R
T
b
SS
SS
SS
a
NC
NC
MODE
A
V
NC
ZZ
DD
A
NC
NC
A
A
U
V
NC
NC
NC
NC
V
DDQ
DDQ
Pin Descriptions
Name
I/O
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A
ADSC
Input-
[17:0]
[17:0]
Synchronous is captured in the address registers. A
are also loaded into the burst counter. When ADSP and
[1:0]
ADSC are both asserted, only ADSP is recognized.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A
Synchronous is captured in the address registers. A
are also loaded into the burst counter. When ADSP and
[1:0]
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE is deasserted HIGH.
1
A
A
Input-
A , A address inputs, These inputs feed the on-chip burst counter as the LSBs as well as being
1 0
[1:0]
Synchronous used to access a particular memory location in the memory array.
Input- Address Inputs used in conjunction with A to select one of the 256K address locations. Sampled
Synchronous at the rising edge of the CLK, if CE , CE , and CE are sampled active, and ADSP or ADSC is active
[17:2]
[1:0]
1
2
3
LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the
Synchronous rising edge. BWS controls DQ and DP , BWS controls DQ and DP . See Write Cycle
BWS
Input-
[1:0]
0
[7:0]
0
1
[15:8]
1
Descriptions table for further details.
ADV
BWE
GW
Input-
Advance input used to advance the on-chip address counter. When LOW the internal burst counter
Synchronous is advanced in a burst sequence. The burst sequence is selected using the MODE input.
Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct
Synchronous a global write, independent of the state of BWE and BWS
. Global writes override byte writes.
[1:0]
CLK
Input-Clock
Clock input. Used to capture all synchronous inputs to the device.
CE
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
1
2
Synchronous and CE to select/deselect the device. CE gates ADSP.
3
1
3
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