Datasheet > CY7C1325B-50AC

CY7C1325B-50AC

更新时间： 2024-02-03 07:48:01

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
17页	336K
描述
Cache SRAM, 256KX18, 11ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1325B-50AC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.83
Base Number Matches：	1

CY7C1325B-50AC 数据手册

PRELIMINARY

CY7C1325B

256K x 18 Synchronous

3.3V Cache RAM

Features

Functional Description

• Supports117-MHzmicroprocessorcachesystems with

zero wait states

• 256K by 18 common I/O

• Fast clock-to-output times

— 7.5 ns (117-MHz version)

The CY7C1325B is a 3.3V, 256K by 18 synchronous cache

RAM designed to interface with high-speed microprocessors

with minimum glue logic. Maximum access delay from clock

rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-

tures the first address in a burst and increments the address

automatically for the rest of the burst access.

• Two-bit wrap-around counter supporting either inter-

leaved or linear burst sequence

• Separate processorand controller address strobes pro-

vide direct interface with the processor and external

cache controller

• Synchronous self-timed write

• Asynchronous output enable

• I/Os capable of 2.5–3.3V operation

• JEDEC-standard pinout

• 100-pin TQFP packaging

• ZZ “sleep” mode

The CY7C1325B allows both interleaved or linear burst se-

quences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses can be initiated with the Processor

Address Strobe (ADSP) or the Cache Controller Address

Strobe (ADSC) inputs. Address advancement is controlled by

the Address Advancement (ADV) input.

A synchronous self-timed write mechanism is provided to sim-

plify the write interface. A synchronous chip enable input and

an asynchronous output enable input provide easy control for

bank selection and output three-state control.

Logic Block Diagram

MODE

(A ,A )

CLK

ADV

ADSC

BURST

COUNTER

CLR

ADSP

ADDRESS

256K X 18

MEMORY

ARRAY

[17:0]

BWE

DQ[15:8]

BYTEWRITE

REGISTERS

DQ[7:0]

BYTEWRITE

REGISTERS

ENABLE

CLK

INPUT

REGISTERS

CLK

SLEEP

CONTROL

[15:0]

[1:0]

Selection Guide

7C1325B-133

7C1325B-117

7C1325B-100

7C1325B-80

7C1325B-50

11.0

Maximum Access Time (ns)

7.5

350

10.0

7.5

350

10.0

8.0

325

10.0

8.5

300

10.0

Maximum Operating Current (mA)

Maximum Standby Current (mA)

250

10.0

Intel and Pentium are registered trademarks of Intel Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

April 5, 2000

12 3 4 5 6 7...17

下载PDF

与CY7C1325B-50AC相关器件

型号	品牌	描述	获取价格	数据表
CY7C1325B-80AC	CYPRESS	Cache SRAM, 256KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
CY7C1325F	CYPRESS	4-Mb (256K x 18) Flow-Through Sync SRAM	获取价格
CY7C1325F-100BGC	CYPRESS	Cache SRAM, 256KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119	获取价格
CY7C1325F-117AC	CYPRESS	4-Mb (256K x 18) Flow-Through Sync SRAM	获取价格
CY7C1325F-117AI	CYPRESS	Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
CY7C1325F-117AXI	CYPRESS	Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格

与CY7C1325B-50AC相关文章

PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

6
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
2024-05-21

5
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
2024-05-21

8
一文带你了解压敏电阻器在直流电路中的过压保护作用
2024-05-21

4

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1325B-50AC

CY7C1325B-50AC 技术参数

CY7C1325B-50AC 数据手册

与CY7C1325B-50AC相关器件

与CY7C1325B-50AC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1325B-50AC

CY7C1325B-50AC 技术参数

CY7C1325B-50AC 数据手册

与CY7C1325B-50AC相关器件

与CY7C1325B-50AC相关文章

您还可以找

您在本页遇到什么问题？