Datasheet > CY7C1325B

CY7C1325B

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	340K
描述
256K x 18 Synchronous 3.3V Cache RAM

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CY7C1325B 数据手册

CY7C1325B

256K x 18 Synchronous

3.3V Cache RAM

Features

Functional Description

• Supports 117-MHzmicroprocessorcachesystems with

zero wait states

• 256K by 18 common I/O

• Fast clock-to-output times

— 7.5 ns (117-MHz version)

The CY7C1325B is a 3.3V, 256K by 18 synchronous cache

RAM designed to interface with high-speed microprocessors

with minimum glue logic. Maximum access delay from clock

rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-

tures the first address in a burst and increments the address

automatically for the rest of the burst access.

• Two-bit wrap-around counter supporting either inter-

leaved or linear burst sequence

• Separate processorand controller address strobespro-

vide direct interface with the processor and external

cache controller

• Synchronous self-timed write

• Asynchronous output enable

• I/Os capable of 2.5–3.3V operation

• JEDEC-standard pinout

• 100-pin TQFP packaging

• ZZ “sleep” mode

The CY7C1325B allows both interleaved or linear burst se-

quences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses can be initiated with the Processor

Address Strobe (ADSP) or the Cache Controller Address

Strobe (ADSC) inputs. Address advancement is controlled by

the Address Advancement (ADV) input.

A synchronous self-timed write mechanism is provided to sim-

plify the write interface. A synchronous chip enable input and

an asynchronous output enable input provide easy control for

bank selection and output three-state control.

Logic Block Diagram

MODE

(A ,A )

CLK

ADV

ADSC

BURST

COUNTER

CLR

ADSP

ADDRESS

256K X 18

MEMORY

ARRAY

[17:0]

BWE

DQ[15:8]

BYTEWRITE

REGISTERS

DQ[7:0]

BYTEWRITE

REGISTERS

ENABLE

CLK

INPUT

REGISTERS

CLK

SLEEP

CONTROL

[15:0]

[1:0]

Selection Guide

7C1325B-117

7C1325B-100

Maximum Access Time (ns)

7.5

350

10.0

8.0

325

10.0

Maximum Operating Current (mA)

Maximum Standby Current (mA)

Intel and Pentium are registered trademarks of Intel Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

September 7, 2000

12 3 4 5 6 7...17

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