Datasheet > 暂无类别数据> CY7C1319AV18-250BZC

CY7C1319AV18-250BZC

更新时间： 2024-11-20 05:19:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
20页	494K
描述
18-Mbit DDR-II SRAM 4-Word Burst Architecture

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CY7C1317AV18

CY7C1319AV18

CY7C1321AV18

PRELIMINARY

18-Mbit DDR-II SRAM 4-Word Burst Architecture

Features

Functional Description

• 18-Mbit density (2M x 8, 1M x 18, 512K x 36)

• 250-MHz clock for high bandwidth

• 4-Word burst for reducing address bus frequency

The CY7C1317AV18/CY7C1319AV18/CY7C1321AV18 are

1.8V Synchronous Pipelined SRAM equipped with DDR-II

(Double Data Rate) architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry

and a two-bit burst counter. Addresses for Read and Write are

latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read

data is driven on the rising edges of C and C if provided, or on

the rising edge of K and K if C/C are not provided. Each

address location is associated with four 8-bit words in the case

of CY7C1317AV18 that burst sequentially into or out of the

device. The burst counter always starts with “00” internally in

the case of CY7C1317AV18. On CY7C1319AV18 and

CY7C1321AV18, the burst counter takes in the last two signif-

icant bits of the external address and bursts four 18-bit words

in the case of CY7C1319AV18, and four 36-bit words in the

case of CY7C1321AV18, sequentially into or out of the device.

Asynchronous inputs include impedance match (ZQ).

Synchronous data outputs (Q, sharing the same physical pins

as the data inputs, D) are tightly matched to the two output

echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR-II SRAM in the

system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

• Double Data Rate (DDR) interfaces (data transferred at

500 MHz) @ 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V_DD

)

• 13 x 15 x 1.4mm 1.0-mm pitch fBGA package, 165-ball

(11 x 15 matrix)

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1317AV18 – 2M x 8

CY7C1319AV18 – 1M x 18

CY7C1321AV18 – 512K x 36

Logic Block Diagram (CY7C1317AV18)

Write Write Write Write

A_(18:0)

Reg Reg Reg

Reg

Address

Output

Logic

CLK

R/W

Gen.

Control

DOFF

Read Data Reg.

V_REF

R/W

NWS_[1:0]

Reg.

Control

Logic

DQ_[7:0]

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05500 Rev. *B

Revised August 11, 2004

12 3 4 5 6 7...20

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与CY7C1319AV18-250BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1319BV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1319BV18-167BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture
CY7C1319BV18-167BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture
CY7C1319BV18-167BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture
CY7C1319BV18-167BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture
CY7C1319BV18-200BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture
CY7C1319BV18-200BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture
CY7C1319BV18-200BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture
CY7C1319BV18-200BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture
CY7C1319BV18-250BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture

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