Datasheet > CY7C1315AV18-167BZC

CY7C1315AV18-167BZC

更新时间： 2024-11-16 09:43:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
22页	327K
描述
18-Mb QDRTM-II SRAM 4-Word Burst Architecture

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CY7C1315AV18-167BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.88
最长访问时间：	0.5 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	167 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.42 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.64 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	13 mm
Base Number Matches：	1

CY7C1315AV18-167BZC 数据手册

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CY7C1311AV18

CY7C1313AV18

CY7C1315AV18

PRELIMINARY

18-Mb QDR™-II SRAM 4-Word Burst Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

— Supports concurrent transactions

The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are

1.8V Synchronous Pipelined SRAMs, equipped with QDR-II

architecture. QDR-II architecture consists of two separate

ports to access the memory array. The Read port has

dedicated Data Outputs to support Read operations and the

Write Port has dedicated Data Inputs to support Write opera-

tions. QDR-II architecture has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Access to each

port is accomplished through a common address bus.

Addresses for Read and Write addresses are latched on

alternate rising edges of the input (K) clock. Accesses to the

QDR-II Read and Write ports are completely independent of

one another. In order to maximize data throughput, both Read

and Write ports are equipped with Double Data Rate (DDR)

interfaces. Each address location is associated with four 8-bit

words (CY7C1311AV18) or 18-bit words (CY7C1313AV18) or

36-bit words (CY7C1315AV18) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K and

K and C and C), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

• 250-MHz Clock for High Bandwidth

• 4-Word Burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 500 MHz) at 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in high

speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in ×8, ×18, and ×36 configurations

• Full data coherancy providing most current data

• Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd)

• 13 × 15 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball

Depth expansion is accomplished with Port Selects for each

(11 × 15 matrix)

port. Port selects allow each port to operate independently.

• Variable drive HSTL output buffers

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

• JTAG 1149.1 Compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1311AV18–2M x 8

CY7C1313AV18–1M x 18

CY7C1315AV18–512K x 36

Logic Block Diagram (CY7C1311AV18)

D_[7:0]

Write Write Write Write

Address

A_(18:0)

Reg Reg Reg

Reg

Address

A_(18:0)

RPS

Control

Logic

CLK

Gen.

DOFF

Read Data Reg.

V_REF

WPS

BWS_[1:0]

Reg.

Control

Logic

Q_[7:0]

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05498 Rev. *A

Revised June 1, 2004

12 3 4 5 6 7...22

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与CY7C1315AV18-167BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1315AV18-200BZC	CYPRESS	获取价格	18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1315AV18-250BZC	CYPRESS	获取价格	18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1315BV18	CYPRESS	获取价格	18-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1315BV18-167BZC	CYPRESS	获取价格	18-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1315BV18-167BZI	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315BV18-167BZXC	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315BV18-167BZXI	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315BV18-200BZC	CYPRESS	获取价格	18-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1315BV18-200BZI	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315BV18-200BZXC	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur

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