CY7C1243KV18/CY7C1245KV18
Pin Definitions (continued)
Pin Name
TDI
I/O
Input
Input
N/A
Pin Description
TDI pin for JTAG.
TMS pin for JTAG.
TMS
NC
Not connected to the die. Can be tied to any voltage level.
NC/72M
NC/144M
NC/288M
VREF
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
Input-
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
reference measurement points.
VDD
VSS
Power supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power supply Power supply inputs for the outputs of the device.
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using K as the output timing reference. On the
subsequent rising edge of K, the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data is
valid 0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
Functional Overview
The CY7C1243KV18, CY7C1245KV18 are synchronous
pipelined burst SRAMs equipped with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR II+ completely eliminates the need to “turn-around” the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of four 18-bit
data transfers in the case of CY7C1243KV18, and four 36-bit
data transfers in the case of CY7C1245KV18, in two clock
cycles.
These devices operate with a read latency of two cycles when
DOFF pin is tied HIGH. When DOFF pin is set LOW or connected
to VSS then device behaves in QDR I mode with a read latency
of one clock cycle.
When the read port is deselected, the CY7C1243KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the positive input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) outputs pass through output registers controlled
by the rising edge of the input clocks (K and K) as well.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also stored
into the write data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The
72 bits of data are then written into the memory array at the
specified location. Therefore, write accesses to the device can
not be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second write request. Write
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1243KV18 is described in the following sections. The
same basic descriptions apply to CY7C1245KV18.
Read Operations
The CY7C1243KV18 is organized internally as four arrays of
512K × 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
Document Number: 001-57832 Rev. *J
Page 6 of 31
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