Datasheet > CY7C1245V18-375BZC

CY7C1245V18-375BZC

更新时间： 2024-02-04 23:37:52

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
28页	647K
描述
QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1245V18-375BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	针数：	165
Reach Compliance Code：	unknown	风险等级：	5.88
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	17 mm	内存密度：	37748736 bit
内存集成电路类型：	QDR SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	认证状态：	COMMERCIAL
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm

CY7C1245V18-375BZC 数据手册

浏览型号CY7C1245V18-375BZC的Datasheet PDF文件第2页

浏览型号CY7C1245V18-375BZC的Datasheet PDF文件第3页

浏览型号CY7C1245V18-375BZC的Datasheet PDF文件第4页

浏览型号CY7C1245V18-375BZC的Datasheet PDF文件第5页

浏览型号CY7C1245V18-375BZC的Datasheet PDF文件第6页

浏览型号CY7C1245V18-375BZC的Datasheet PDF文件第7页

CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

36-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.0 cycles:

CY7C1241V18 – 4M x 8

CY7C1256V18 – 4M x 9

CY7C1243V18 – 2M x 18

CY7C1245V18 – 1M x 36

■ 300 MHz to 375 MHz clock for high bandwidth

■ 4-Word Burst for reducing address bus frequency

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 750 MHz) at 375 MHz

Functional Description

■ Read latency of 2.0 clock cycles

The CY7C1241V18, CY7C1256V18, CY7C1243V18, and

CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with Quad Data Rate-II+ (QDR-II+) architecture.

QDR-II+ architecture consists of two separate ports to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR-II+ architecture has

separate data inputs and data outputs to completely eliminate

the need to “turn around” the data bus required with common IO

devices. Each port can be accessed through a common address

bus. Read and write addresses are latched on alternate rising

edges of the input (K) clock. Accesses to the QDR-II+ read and

write ports are completely independent of one another. To

maximize data throughput, both read and write ports are

equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with four 8-bit words

(CY7C1241V18), 9-bit words (CY7C1256V18), 18-bit words

(CY7C1243V18), or 36-bit words (CY7C1245V18), that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate Port Selects for depth expansion

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency providing most current data

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

Depth expansion is accomplished with Port Selects for each port.

Port selects enable each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Delay Lock Loop (DLL) for accurate data placement

Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

375 MHz

333 MHz

333

300 MHz

300

Unit

MHz

375

1240

1120

1040

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting

DDQ

= 1.4V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-06365 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 12, 2008

[+] Feedback

12 3 4 5 6 7...28

中文翻译

下载PDF

与CY7C1245V18-375BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1245V18-375BZI	CYPRESS	获取价格	QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C12461KV18	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246KV18	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-300BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-300BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-300BZXC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-300BZXI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-333BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-333BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

与CY7C1245V18-375BZC相关文章

压敏电阻器在直流电路中的过压保护应用探讨
2024-06-07

2
电感耐压值及其与电感大小的关系
2024-06-07

5
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
2024-06-07

4
DS1307资料解析：特性、引脚说明、替代推荐
2024-06-07

3

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1245V18-375BZC

CY7C1245V18-375BZC 技术参数

CY7C1245V18-375BZC 数据手册

与CY7C1245V18-375BZC相关器件

与CY7C1245V18-375BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1245V18-375BZC

CY7C1245V18-375BZC 技术参数

CY7C1245V18-375BZC 数据手册

与CY7C1245V18-375BZC相关器件

与CY7C1245V18-375BZC相关文章

您还可以找

您在本页遇到什么问题？