Datasheet > CY7C1245V18-375BZI

CY7C1245V18-375BZI

更新时间： 2023-02-26 15:01:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	647K
描述
QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165

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数据手册

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CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

36-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.0 cycles:

CY7C1241V18 – 4M x 8

CY7C1256V18 – 4M x 9

CY7C1243V18 – 2M x 18

CY7C1245V18 – 1M x 36

■ 300 MHz to 375 MHz clock for high bandwidth

■ 4-Word Burst for reducing address bus frequency

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 750 MHz) at 375 MHz

Functional Description

■ Read latency of 2.0 clock cycles

The CY7C1241V18, CY7C1256V18, CY7C1243V18, and

CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with Quad Data Rate-II+ (QDR-II+) architecture.

QDR-II+ architecture consists of two separate ports to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR-II+ architecture has

separate data inputs and data outputs to completely eliminate

the need to “turn around” the data bus required with common IO

devices. Each port can be accessed through a common address

bus. Read and write addresses are latched on alternate rising

edges of the input (K) clock. Accesses to the QDR-II+ read and

write ports are completely independent of one another. To

maximize data throughput, both read and write ports are

equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with four 8-bit words

(CY7C1241V18), 9-bit words (CY7C1256V18), 18-bit words

(CY7C1243V18), or 36-bit words (CY7C1245V18), that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate Port Selects for depth expansion

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency providing most current data

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

Depth expansion is accomplished with Port Selects for each port.

Port selects enable each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Delay Lock Loop (DLL) for accurate data placement

Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

375 MHz

333 MHz

333

300 MHz

300

Unit

MHz

375

1240

1120

1040

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting

DDQ

= 1.4V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-06365 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 12, 2008

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与CY7C1245V18-375BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C12461KV18	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246KV18	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-300BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-300BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-300BZXC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-300BZXI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-333BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-333BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18-333BZXC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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