Datasheet > CY7C1156V18-300BZXC

CY7C1156V18-300BZXC

更新时间： 2024-02-23 17:10:30

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	1159K
描述
18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

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技术参数
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CY7C1156V18-300BZXC 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	300 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	9
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	2MX9	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.201 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.663 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	13 mm

CY7C1156V18-300BZXC 数据手册

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CY7C1141V18

CY7C1156V18

CY7C1143V18

CY7C1145V18

Pin Definitions

Pin Name

Pin Description

Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.

D_[x:0]

Input-

Synchronous CY7C1141V18−D_[7:0]

CY7C1156V18−D_[8:0]

CY7C1143V18−D_[17:0]

CY7C1145V18−D_[35:0]

WPS

Input-

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active,

Synchronous a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes

D_[x:0]to be ignored.

Input-

Nibble Write Select 0, 1 − Active LOW.(CY7C1141V18 Only) Sampled on the rising edge of the K

NWS₀, NWS₁

Synchronous and K clocks during write operations. This is used to select the nibble that is written into the device

NWS₀controls D_[3:0]and NWS₁controls D_[7:4]

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write

Select causes the corresponding nibble of data to be ignored and not written into the device.

BWS₀, BWS₁,

BWS₂, BWS₃

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks

Synchronous during write operations. This is used to select the byte that is written into the device during the current

portion of the write operations. Bytes not written remain unaltered.

CY7C1156V18 − BWS₀controls D_[8:0]

CY7C1143V18 BWS controls D_[8:0]and BWS₁controls D_[17:9]

−

CY7C1145V18 BWS⁰controls D_[8:0], BWS₁controls D_[17:9], BWS₂controls D_[26:18],and BWS₃

−

controls D_[35:27]

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

causes the corresponding byte of data to be ignored and not written into the device.

Input-

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.

Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is

organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1141V18, 2M x 9 (4 arrays each of 512K

x 9) for CY7C1156V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1143V18, and 512K x 36 (4

arrays each of 128K x 36) for CY7C1145V18. Therefore, only 19 address inputs are needed to access

the entire memory array of CY7C1141V18 and CY7C1156V18, 18 address inputs for CY7C1143V18

and 17 address inputs for CY7C1145V18. These inputs are ignored when the appropriate port is

deselected.

Q_[x:0]

Outputs-

Data Output signals. These pins drive out the requested data during a read operation. Valid data is

Synchronous driven out on the rising edge of both the K and K clocks during read operations or K and K when in

single clock mode. When the read port is deselected, Q_[x:0]are automatically tri-stated.

CY7C1141V18−Q_[7:0]

CY7C1156V18−Q_[8:0]

CY7C1143V18−Q_[17:0]

CY7C1145V18−Q_[35:0]

RPS

Input-

Read Port Select − Active LOW. Sampled on the rising edge of Positive Input Clock (K). When

Synchronous active, a read operation is initiated. Deasserting causes the read port to be deselected. When

deselected, the pending access is enabled to complete and the output drivers are automatically

tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four

sequential transfers.

QVLD

Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

indicator

CQ.

Input-

Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q_[x:0]when in single clock mode. All accesses are initiated on the rising

edge of K.

Input-

Clock

Negative Input Clock Input. K is used to capture synchronous inputs presented to the device and

to drive out data through Q_[x:0]when in single clock mode.

Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

on page 23.

Document Number: 001-06583 Rev. *C

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CY7C1156V18-300BZXI	CYPRESS	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu	获取价格
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CY7C1156V18-333BZI	CYPRESS	QDR SRAM, 2MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165	获取价格
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