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CY7C1150V18-375BZXI PDF预览

CY7C1150V18-375BZXI

更新时间: 2024-02-17 08:21:13
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器双倍数据速率
页数 文件大小 规格书
27页 1126K
描述
18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1150V18-375BZXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA, BGA165,11X15,40针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):375 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B165JESD-609代码:e1
长度:15 mm内存密度:18874368 bit
内存集成电路类型:DDR SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:165字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:1.5/1.8,1.8 V
认证状态:Not Qualified座面最大高度:1.4 mm
最大待机电流:0.29 A最小待机电流:1.7 V
子类别:SRAMs最大压摆率:1.02 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:13 mm
Base Number Matches:1

CY7C1150V18-375BZXI 数据手册

 浏览型号CY7C1150V18-375BZXI的Datasheet PDF文件第4页浏览型号CY7C1150V18-375BZXI的Datasheet PDF文件第5页浏览型号CY7C1150V18-375BZXI的Datasheet PDF文件第6页浏览型号CY7C1150V18-375BZXI的Datasheet PDF文件第8页浏览型号CY7C1150V18-375BZXI的Datasheet PDF文件第9页浏览型号CY7C1150V18-375BZXI的Datasheet PDF文件第10页 
CY7C1146V18  
CY7C1157V18  
CY7C1148V18  
CY7C1150V18  
Pin Definitions (continued)  
Pin Name  
DOFF  
IO  
Pin Description  
Input  
DLL Turn Off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The  
timings in the DLL turned off operation are different from those listed in this data sheet. For normal  
operation, connect this pin to a pull up through a 10 Kor less pull up resistor. The device behaves  
in DDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to  
167 MHz with DDR-I timing.  
TDO  
Output  
Input  
Input  
Input  
N/A  
TDO for JTAG.  
TCK  
TCK pin for JTAG.  
TDI  
TDI pin for JTAG.  
TMS  
TMS pin for JTAG.  
NC  
Not connected to the die. Tie to any voltage level.  
Not connected to the die. Tie to any voltage level.  
Not connected to the die. Tie to any voltage level.  
Not connected to the die. Tie to any voltage level.  
Not connected to the die. Tie to any voltage level.  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and  
NC/36M  
NC/72M  
NC/144M  
NC/288M  
VREF  
N/A  
N/A  
N/A  
N/A  
Input-  
Reference AC measurement points.  
VDD  
VSS  
Power Supply Power supply inputs to the core of the device.  
Ground  
Ground for the device.  
VDDQ  
Power Supply Power supply inputs for the outputs of the device.  
Document Number: 001-06621 Rev. *C  
Page 7 of 27  

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