Datasheet > CY7C09389V

CY7C09389V

更新时间： 2024-11-07 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	760K
描述
3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

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中文翻译

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CY7C09389V 数据手册

CY7C09269V CY7C09279V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K/64K

Synchronous Dual-Port Static RAM

x 16/18

1CY7C025/0251

CY7C09269V/79V/89V

CY7C09369V/79V/89V

3.3V 16K/32K/64K x 16/18

Synchronous Dual-Port Static RAM

• High-speed clock to data access 6.5^{[1, 2]}/7.5^[2]/9/12 ns

Features

(max.)

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• 3.3V low operating power

— Active = 115 mA (typical)

• 6 Flow-Through/Pipelined devices

— 16K x 16/18 organization (CY7C09269V/369V)

— 32K x 16/18 organization (CY7C09279V/379V)

— 64K x 16/18 organization (CY7C09289V/389V)

• 3 Modes

— Standby = 10 µA (typical)

• Fully synchronous interface for easier operation

• Burst counters increment addresses internally

— Shorten cycle times

— Minimize bus noise

— Flow-Through

— Supported in Flow-Through and Pipelined modes

• Dual Chip Enables for easy depth expansion

• Upper and Lower Byte Controls for Bus Matching

• Automatic power-down

— Pipelined

— Burst

• Pipelined output mode on both ports allows fast

100-MHz operation

• Commercial and Industrial temperature ranges

• Pb-Free 100-pin TQFP Package Available

• 0.35-micron CMOS for optimum speed/power

Logic Block Diagram

R/W_L

UB_L

R/W_R

UB_R

CE_0L

CE_0R

CE_1L

LB_L

CE_1R

LB_R

0/1

OE_L

OE_R

1b 0b 1a 0a

0a 1a 0b 1b

0/1

FT/Pipe_L

FT/Pipe_R

8/9

[3]

I/O_8/9L–I/O_15/17L

I/O_8/9R–I/O_15/17R

I/O

Control

I/O

Control

[4]

7/8L

[4]

7/8R

I/O_0L–I/O

I/O_0R–I/O

14/15/16

[5]

13/14/15L

[5]

A_0L–A

–A

13/14/15R

Counter/

Address

Decode

Counter/

Address

Decode

CLK_L

ADS_L

CLK_R

True Dual-Ported

ADS_R

RAM Array

CNTEN_L

CNTEN_R

CNTRST_L

CNTRST_R

Notes:

1. Call for availability.

2. See page 6 for Load Conditions.

3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.

4. I/O –I/O for x16 devices. I/O –I/O for x18 devices.

5. A –A for 16K; A –A for 32K; A –A for 64K devices.

Cypress Semiconductor Corporation

Document #: 38-06056 Rev. *B

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised April 6, 2005

12 3 4 5 6 7...19

中文翻译

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与CY7C09389V相关器件

型号	品牌	获取价格	描述	数据表
CY7C09389V-12AC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09389V-12AC	ROCHESTER	获取价格	64KX18 DUAL-PORT SRAM, 12ns, PQFP100, PLASTIC, MS-026, TQFP-100
CY7C09389V-12AXC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09389V-12AXC	ROCHESTER	获取价格	64KX18 DUAL-PORT SRAM, 12ns, PQFP100, LEAD FREE, PLASTIC, MS-026, TQFP-100
CY7C09389V-12AXCT	CYPRESS	获取价格	Dual-Port SRAM, 64KX18, 12ns, CMOS, PQFP100, LEAD FREE, PLASTIC, MS-026, TQFP-100
CY7C09389V-6AC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09389V-6AC	ROCHESTER	获取价格	64KX18 DUAL-PORT SRAM, 6.5ns, PQFP100, PLASTIC, MS-026, TQFP-100
CY7C09389V-6AXC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09389V-6AXC	ROCHESTER	获取价格	64KX18 DUAL-PORT SRAM, 6.5ns, PQFP100, LEAD FREE, PLASTIC, MS-026, TQFP-100
CY7C09389V-7AC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

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