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CY7C09369V-9AC PDF预览

CY7C09369V-9AC

更新时间: 2024-02-05 00:37:30
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 静态存储器内存集成电路
页数 文件大小 规格书
20页 1231K
描述
16KX18 DUAL-PORT SRAM, 9ns, PQFP100, PLASTIC, MS-026, TQFP-100

CY7C09369V-9AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, MS-026, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.62最长访问时间:9 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK):67 MHz
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:294912 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.00025 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.23 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

CY7C09369V-9AC 数据手册

 浏览型号CY7C09369V-9AC的Datasheet PDF文件第1页浏览型号CY7C09369V-9AC的Datasheet PDF文件第3页浏览型号CY7C09369V-9AC的Datasheet PDF文件第4页浏览型号CY7C09369V-9AC的Datasheet PDF文件第5页浏览型号CY7C09369V-9AC的Datasheet PDF文件第6页浏览型号CY7C09369V-9AC的Datasheet PDF文件第7页 
CY7C09269V/79V/89V  
CY7C09369V/79V/89V  
3.3V 16K/32K/64K x 16/18  
Synchronous Dual-Port Static RAM  
3.3V low operating power:  
Active = 115 mA (typical)  
Standby = 10 μA (typical)  
Features  
True dual-ported memory cells that allow simultaneous access  
of the same memory location  
Fully synchronous interface for easier operation  
Six flow through/pipelined devices:  
Burst counters increment addresses internally:  
Shorten cycle times  
Minimize bus noise  
16K x 16/18 organization (CY7C09269V/369V)  
32K x 16/18 organization (CY7C09279V/379V)  
64K x 16/18 organization (CY7C09289V/389V)  
Supported in flow through and pipelined modes  
Three modes:  
Flow through  
Pipelined  
Burst  
Dual chip enables easy depth expansion  
Upper and lower byte controls for bus matching  
Automatic power down  
Pipelined output mode on both ports allows fast 100 MHz  
operation  
Commercial and industrial temperature ranges  
Pb-Free 100-pin TQFP package available  
0.35 micron CMOS for optimum speed and power  
High speed clock to data access: 6.5[1, 2], 7.5[2], 9, 12 ns (max)  
Logic Block Diagram  
R/WL  
R/WR  
UB  
UB  
R
L
CE  
CE  
CE  
CE  
0L  
1L  
0R  
1R  
1
1
0
0
0/1  
0/1  
LB  
LB  
L
R
OE  
OE  
L
R
1b 0b 1a 0a  
0a 1a 0b 1b  
0/1  
b
a
a
b
0/1  
FT/PipeL  
FT/PipeR  
8/9  
8/9  
8/9  
8/9  
[3]  
[3]  
I/O8/9L–I/O15/17L  
I/O8/9R–I/O15/17R  
I/O  
Control  
I/O  
Control  
[4]  
[4]  
I/O0L–I/O7/8L  
I/O0R–I/O7/8R  
14/15/16  
A
0L–A  
14/15/16 A0RA[5]  
[5]  
13/14/15L  
13/14/15R  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLK  
CLK  
ADS  
L
R
R
R
R
True Dual-Ported  
ADS  
L
RAM Array  
CNTEN  
CNTEN  
CNTRST  
L
CNTRST  
L
Notes  
1. Call for availability.  
2. See page 6 for Load Conditions.  
3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
8
15  
9
17  
4. I/O –I/O for x16 devices. I/O –I/O for x18 devices.  
0
7
0
8
5. A –A for 16K; A –A for 32K; A –A for 64K devices.  
0
13  
0
14  
0
15  
Cypress Semiconductor Corporation  
Document #: 38-06056 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 25, 2009  
[+] Feedback  

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