Datasheet > CY7C09369V-7AI

CY7C09369V-7AI

更新时间： 2024-02-04 05:56:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	348K
描述
3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

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技术参数
数据手册

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CY7C09369V-7AI 技术参数

生命周期：	Active	零件包装代码：	QFP
包装说明：	LEAD FREE, PLASTIC, MS-026, TQFP-100	针数：	100
Reach Compliance Code：	unknown	风险等级：	5.78
最长访问时间：	7.5 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e3/e4
长度：	14 mm	内存密度：	294912 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	18
功能数量：	1	端子数量：	100
字数：	16384 words	字数代码：	16000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	16KX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	认证状态：	COMMERCIAL
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN/NICKEL PALLADIUM GOLD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

CY7C09369V-7AI 数据手册

CY7C09269V/79V/89V

CY7C09369V/79V/89V

Pin Definitions

Left Port

A_0L–A_15L

ADS_L

Right Port

Description

A_0R–A_15R

Address Inputs (A₀–A₁₄for 32K, A₀–A₁₃for 16K devices).

ADS_R

Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to

access the part using an externally supplied address. Asserting this signal LOW also loads the

burst counter with the address present on the address pins.

CE_0L,CE_1L

CE_0R,CE_1R

Chip Enable Input. To select either the left or right port, both CE₀AND CE₁must be asserted

to their active states (CE₀≤ V_ILand CE₁≥ V_IH).

CLK_L

CLK_R

Clock Signal. This input can be free running or strobed. Maximum clock input rate is f_MAX.

CNTEN_L

CNTEN_R

Counter Enable Input. Asserting this signal LOW increments the burst address counter of its

respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted

LOW.

CNTRST_L

CNTRST_R

Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-

tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.

I/O_0L–I/O_17L

I/O_0R–I/O_17RData Bus Input/Output (I/O₀–I/O₁₅for x16 devices).

LB_L

LB_R

Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the

lower byte. (I/O₀–I/O₈for x18, I/O₀–I/O₇for x16) of the memory array. For read operations both

the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.

UB_L

OE_L

UB_R

OE_R

Upper Byte Select Input. Same function as LB, but to the upper byte (I/O_8/9L–I/O_15/17L).

Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read

operations.

R/W_L

R/W_R

Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.

For read operations, assert this pin HIGH.

FT/PIPE_L

FT/PIPE_R

Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.

For pipelined mode operation, assert this pin HIGH.

GND

Ground Input.

No Connect.

Power Input.

V_CC

Output Current into Outputs (LOW)............................. 20 mA

Maximum Ratings

Static Discharge Voltage ........................................... >1100V

Latch-Up Current...................................................... >200mA

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature................................. –65°C to +150°C

Operating Range

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Ambient

Supply Voltage to Ground Potential............... –0.5V to +4.6V

Range

Commercial

Industrial

Temperature

0°C to +70°C

–40°C to +85°C

V_CC

DC Voltage Applied to

Outputs in High Z State ...........................–0.5V to V_CC+0.5V

3.3V ± 300 mV

DC Input Voltage......................................–0.5V to V_CC+0.5V

Document #: 38-06056 Rev. **

Page 4 of 19

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与CY7C09369V-7AI相关器件

型号	品牌	获取价格	描述	数据表
CY7C09369V-7AXC	ROCHESTER	获取价格	16KX18 DUAL-PORT SRAM, 7.5ns, PQFP100, LEAD FREE, PLASTIC, MS-026, TQFP-100
CY7C09369V-9AC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09369V-9AC	ROCHESTER	获取价格	16KX18 DUAL-PORT SRAM, 9ns, PQFP100, PLASTIC, MS-026, TQFP-100
CY7C09369V-9ACT	CYPRESS	获取价格	Dual-Port SRAM, 16KX18, 9ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
CY7C09369V-9AI	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09369V-9AXC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09369V-9AXCT	CYPRESS	获取价格	暂无描述
CY7C09379	CYPRESS	获取价格	32K/64K X 16/18 Synchronous Dual Port Static RAM
CY7C09379-10AI	CYPRESS	获取价格	Multi-Port SRAM, 64KX9, 10ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C09379-12AC	CYPRESS	获取价格	32K/64K X 16/18 Synchronous Dual Port Static RAM

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